R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 889

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.
Configuration Mode
2. Mailboxes are comprised of RAMs, therefore, please initialize all the mailboxes enabled by MBC.
3. It takes approximately 25 peripheral bus cycles for GSR[3] to be cleared to 0.
4. If there is no TXPR set, RCAN-ET will receive the next incoming message.
If it loses the arbitration, it will become a receiver.
If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.
IRR[0] = 1, GSR[3] = 1 (automatically)
(automatically in hardware reset only)
RTR, IDE, MBC, MBIMR, DART,
(STD-ID, EXT-ID, LAFM, DLC,
ATX, NMC, Message-Data)*
Clear Required IMR Bits
Power On/SW Reset*
Set Bit Timing (BCR)
Configure MCR[15]
clear IRR[0] Bit
Mailbox Setting
Clear MCR[0]
MCR[0] = 1
Section 19 Controller Area Network (RCAN-ET) [R5S72611] [R5S72613]
Figure 19.6 Reset Sequence
1
2
Receive*
Rev. 2.00 Sep. 07, 2007 Page 857 of 1312
Detect 11 recessive bits and
RCAN-ET is in Tx_Rx Mode
Set TXPR to start transmission
or stay idle to receive
Join the CAN bus activity
4
GSR[3] = 0?
Yes
Transmission_Reception
(Tx_Rx) Mode
REJ09B0320-0200
Transmit*
No*
4
3