R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 949
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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20.3.17 IEBus Transmit Interrupt Enable Register (IEIET)
IEIET enables/disables interrupts for sources such as transmit start, transmit normal completion,
and transmit error completion in IETSR.
IEIET is initialized by a power-on reset or in deep standby.
Bit
7
6
5
4
3
Bit Name
TXSE
TXFE
TXEALE
Initial value:
Initial
Value
0
0
0
0
0
R/W:
Bit:
R/W
R
R/W
R/W
R
R/W
—
R
7
0
TXSE
R/W
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Transmit Start Interrupt Enable
Enables/disables a transmit start (TXS) interrupt.
0: Disables a transmit start (TXS) interrupt
1: Enables a transmit start (TXS) interrupt
Transmit Normal Completion Interrupt Enable
Enables/disables a transmit normal completion (TXF)
interrupt.
0: Disables a transmit normal completion (TXF)
1: Enables a transmit normal completion (TXF) interrupt
Reserved
This bit is always read as 0. The write value should
always be 0.
Arbitration Loss Interrupt Enable
Enables/disables an arbitration loss (TXEAL) interrupt.
0: Disables an arbitration loss (TXEAL) interrupt
1: Enables an arbitration loss (TXEAL) interrupt
TXFE
R/W
Section 20 IEBus
5
0
interrupt
—
R
4
0
EALE
R/W
TX
3
0
TTMEE
Rev. 2.00 Sep. 07, 2007 Page 917 of 1312
R/W
TXE
TM
2
0
Controller (IEB) [R5S72612] [R5S72613]
EROE
R/W
TX
1
0
ACKE
R/W
TXE
0
0
REJ09B0320-0200
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