R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 916

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 IEBus
(a)
The master unit outputs the message length bits and the parity bit. When the parity is even, the
slave unit returns an acknowledgement and enters the following data field. Note that the slave unit
does not return an acknowledgement in broadcast communications.
When the parity is odd, the slave unit decides that the message length field is not correctly
received, does not return an acknowledgement, and returns to the waiting (monitor) state. In this
case, the master unit also returns to the waiting state and communications end.
(b) Master Reception
The slave unit outputs the message length bits and parity bit. When even parity is confirmed, the
master unit returns an acknowledgement.
When the parity is not correct, the master unit decides that the message length bits are not
correctly received, does not return an acknowledgement, and returns to the waiting state. In this
case, the slave unit also returns to the waiting state and communications end.
(6)
The data field is a field for data transmission/reception to and from the slave unit. The master unit
transmits/receives data to and from the slave unit using the data field. The data field is comprised
of data bits, a parity bit, and an acknowledge bit.
The data bits consist of eight bits and the MSB is output first.
The parity and acknowledge bits are output following the data bits from the master unit and slave
unit, respectively.
Broadcast communications are performed only for the transmission of the master unit. In this case,
the acknowledge bit is ignored. Operations in master transmission and master reception are
described below.
Rev. 2.00 Sep. 07, 2007 Page 884 of 1312
REJ09B0320-0200
Master Transmission
Data Field
TM
Controller (IEB) [R5S72612] [R5S72613]