R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 329

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
12 to 10 
9, 8
7, 6
5
4 to 2
1, 0
Bit Name
OMST[1:0]

SHER

SHMST
[1:0]
Initial
Value
All 0
00
All 0
0
All 0
00
R/W
R
R/W
R
R
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Master
These bits indicate the bus master that accessed other
buses when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Illegal Address Access
This bit indicates that an illegal address access was
made on peripheral bus (2) when the first bus error
occurred.
0: Illegal address access not made
1: Illegal address access made
Reserved
These bits are always read as 0. The write value
should always be 0.
Bus Master
These bits indicate the bus master that accessed
peripheral bus (2) when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Rev. 2.00 Sep. 07, 2007 Page 297 of 1312
Section 10 Bus Monitor
REJ09B0320-0200