R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 650

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 13 8-Bit Timers (TMR)
13.5.6
The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure
13.11 shows the timing of this operation.
13.6
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode).
13.6.1
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
(1)
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
(2)
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
Rev. 2.00 Sep. 07, 2007 Page 618 of 1312
REJ09B0320-0200
16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by
the TMRI0 pin has been set.
cleared independently.
Setting of Compare Match Flags
Counter Clear Specification
Timing of Overflow Flag (OVF) Setting
Operation with Cascaded Connection
16-Bit Counter Mode
Pφ
TCNT
Overflow signal
OVF
Figure 13.11 Timing of OVF Setting
H'FF
H'00