R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 34

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R5S72611

Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 1 Overview
Table 1.1
Rev. 2.00 Sep. 07, 2007 Page 2 of 1312
REJ09B0320-0200
Item
CPU
SH7261 Group Features
Features
Renesas Technology original SuperH architecture
Compatible with SH-1 and SH-2 at object code level
32-bit internal data bus
Support of an abundant register-set
 Sixteen 32-bit general registers
 Four 32-bit control registers
 Four 32-bit system registers
 Register bank for high-speed response to interrupts
RISC-type instruction set (upward compatible with SH series)
 Instruction length: 16-bit fixed-length basic instructions for
 Load/store architecture
 Delayed branch instructions
 Instruction set based on C language
Superscalar architecture to execute two instructions at one time
including FPU
Instruction execution time: Up to two instructions/cycle
Address space: 4 Gbytes
Internal multiplier
Five-stage pipeline
Harvard architecture
improved code efficiency and 32-bit instructions for high
performance and usability

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