R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 922

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20 IEBus
(2)
In the case of data read (H'3, H'7), data in the data buffer of the slave unit is read in the master
unit. In the case of data write (H'B or H'F) or command write (H'A or H'E), data received in the
slave unit is processed in accordance with the operation specification of the slave unit.
Notes: 1. The user can select data and commands freely in accordance with the system.
(3)
In the case of the locked address read (H'4 or H'5), the address (12 bits) of the master unit which
issues the lock instruction is configured in bytes as shown in figure 20.3.
(4)
The lock function is used for message transfer over multiple communications frames. A locked
unit receives data only from the unit which locked it.
Locking and unlocking are described below.
(a)
When an acknowledge bit of 0 in the message length field is transmitted/received with the control
bits (H'3, H'A, H'B) indicating the lock operation, and then the communications frame is
completed before completion of data transmission/reception for the number of bytes specified by
the message length bits, the slave unit is locked by the master unit. In this case, the bit (bit 2)
relevant to locking in the byte data indicating the slave status is set to 1.
Lock is set only when the number of data exceeds the maximum number of transfer bytes in one
frame. Lock is not set by other error terminations.
Rev. 2.00 Sep. 07, 2007 Page 890 of 1312
REJ09B0320-0200
SDA
SCL
Data Command Transfer (Control Bits: Read (H'3, H'7), Write (H'A, H'B, H'E, H'F))
Locked Address Read (Control Bits: H′4, H′5)
Locking/Unlocking (Control Bits: Setting (H'3, H'A, H'B), Cancellation: (H'6))
Locking
S
2. H'3, H'A, or H'B may lock depending on the communications condition and status.
SLA
TM
1-7
Controller (IEB) [R5S72612] [R5S72613]
R/W
8
Figure 20.3 Locked Address Configuration
9
A
1-7
DATA
8
A
9
1-7
DATA
8
A
9
P