R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 268

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 Bus State Controller (BSC)
[Legend]
x: Don't care
Rev. 2.00 Sep. 07, 2007 Page 236 of 1312
REJ09B0320-0200
Bit
11 to 9
8
7 to 3
2 to 0
Bit Name
DPCG[2:0] Undefined R/W
DWR

DCL[2:0]
Initial
Value
0
All 0
Undefined R/W
R/W
R
R/W
Description
Row Precharge Interval Setting
These bits specify the minimum number of cycles that
must elapse between the SDRAM deactivation
command (PRA) and the next valid command.
000: 1 cycles
111: 8 cycles
Write Recovery Interval Setting
This bit specifies the minimum interval that must elapse
between the SDRAM write command (WRITE) and
deactivation (PRA).
0: 1 cycles
1: 2 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Controller Column Latency Setting
These bits specify the column latency of the SDRAM
controller. This setting only affects the latency setting
on the SDRAM controller side. To specify the column
latency for externally connected SDRAM it is
necessary to use the separate SDRAMm mode register
(SDmMOD), which is described below.
000: Setting prohibited
001: 1 cycles
010: 2 cycles
011: 3 cycles
1xx: Setting prohibited
: