R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 259

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

9.4.8
SDRFCNT1 controls auto-refresh operation.
Bit
31 to 17 
16
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAM Refresh Control Register 1 (SDRFCNT1)
Bit Name
DRFEN
R/W
31
15
—
—
R
0
R/W
DREFW[3:0]
30
14
—
—
R
0
R/W
29
13
Initial
Value
All 0
0
—
—
R
0
R/W
28
12
—
—
R
0
R/W
27
11
—
—
R
0
R/W
R
R/W
R/W
26
10
—
—
R
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Auto-Refresh Operation Enable
This bit controls auto-refresh operation for all channels
simultaneously. When DRFEN is cleared to 0, auto-
refresh operation does not take place. Auto-refresh
operates when DRFEN is set to 1. Clearing this bit to 0
while auto-refresh is enabled causes DRFEN to be
cleared to 0, and auto-refresh operation to halt, after
the end of the next auto-refresh cycle. Setting this bit to
1 while auto-refresh is enabled causes auto-refresh
operation to commence as soon as DRFEN is set to 1,
and refresh requests are then generated at fixed
intervals determined by a counter. The interval at which
refresh requests are generated is determined by the
set value of the auto-refresh request interval setting
(DRFC) bits. Refresh requests are not accepted while
SDRAM is being accessed; they must wait until the
access completes. If a SDRAM access and refresh
request are generated at the same time, the refresh
request takes precedence.
0: Auto-refresh disabled
1: Auto-refresh enabled
R/W
25
—
—
R
0
9
R/W
24
—
—
R
0
8
R/W
23
—
—
R
0
7
Rev. 2.00 Sep. 07, 2007 Page 227 of 1312
DRFC[11:0]
R/W
22
—
—
R
0
6
Section 9 Bus State Controller (BSC)
R/W
21
—
—
R
0
5
R/W
20
—
—
R
0
4
R/W
19
—
—
R
0
3
REJ09B0320-0200
R/W
18
—
—
R
0
2
R/W
17
—
R
—
0
1
DRFEN
R/W
R/W
16
—
0
0