R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 965

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.5.4
Figure 20.11 shows the flowchart for master reception.
[IESA1, IESA2 register setting]
Broadcast/normal selection
[IEMCR register setting]
Retransfer counts
Slave address
Initial setting
Master Reception
Control bits
Start
Figure 20.11 Flowchart for Master Reception
Master communications
[IECMR register setting]
(IERB001 to IERB128)
Receive start interrupt
IERSR[RXBSY] clear
Receive completion
Interrupt processing
Interrupt processing
IERSR[RXS] clear
IERSR[RXF] clear
Receive data read
request command
Section 20 IEBus
interrupt
End
Receive start interrupt (RXS)
Receive completion interrupt (RXF)
Rev. 2.00 Sep. 07, 2007 Page 933 of 1312
TM
Receive error interrupt
(RXE***)
Receive error interrupt
(RXE***)
Controller (IEB) [R5S72612] [R5S72613]
IERSR[RXE***] clear
IETSR[TXE***] clear
Interrupt processing
REJ09B0320-0200