R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 70

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2 CPU
2.3.3
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx:
• mmmm: Source register
• nnnn:
• iiii:
• dddd:
Table 2.9
Rev. 2.00 Sep. 07, 2007 Page 38 of 1312
REJ09B0320-0200
Instruction Formats
0 format
15
n format
15
xxxx
xxxx
nnnn
xxxx
Instruction Format
Instruction Formats
Instruction code
Destination register
Immediate data
Displacement
xxxx xxxx
xxxx
xxxx
0
0
Source
Operand
—
—
Control register or
system register
R0 (Register direct) nnnn: Register
Control register or
system register
mmmm: Register
direct
R15 (Register
indirect with post-
increment)
R0 (Register direct) nnnn: (Register
Destination
Operand
—
nnnn: Register
direct
nnnn: Register
direct
direct
nnnn: Register
indirect with pre-
decrement
R15 (Register
indirect with pre-
decrement)
nnnn: Register
direct
indirect with post-
increment)
Example
NOP
MOVT
STS
DIVU
STC.L SR,@-Rn
MOVMU.L
MOVMU.L
MOV.L R0,@Rn+
Rn
MACH,Rn
R0,Rn
Rm,@-R15
@R15+,Rn