R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 202

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.3.3
BDR is a 32-bit readable/writable register. The control bits CD[1:0] in the break bus cycle register
(BBR) select one of the two data buses for a break condition. BDR is initialized to H'00000000 by
a power-on reset or in deep standby, but retains its previous value by a manual reset or in software
standby mode or sleep mode.
Notes: 1. Set the operand size when specifying a value on a data bus as the break condition.
Rev. 2.00 Sep. 07, 2007 Page 170 of 1312
REJ09B0320-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. When the byte size is selected as a break condition, the same byte data must be set in
Break Data Register (BDR)
BD31 BD30 BD29 BD28 BD27 BD26 BD25 BD24 BD23 BD22 BD21 BD20 BD19 BD18 BD17 BD16
BD15 BD14 BD13 BD12 BD11 BD10 BD9
Bit Name
BD31 to BD0 All 0
R/W
R/W
bits 31 to 24, 23 to 16, 15 to 8, and 7 to 0 in BDR as the break data. Similarly, when the
word size is selected, the same word data must be set in bits 31 to 16 and 15 to 0.
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W
R/W
R/W
R/W
26
10
0
0
Description
Break Data Bits
Store data which specifies a break condition.
If the I bus is selected in BBR, specify the break data
on IDB in bits BD31 to BD0.
If the C bus is selected in BBR, specify the break data
on MDB in bits BD31 to BD0.
R/W
R/W
25
0
9
0
R/W
BD8
R/W
24
0
8
0
R/W
BD7
R/W
23
0
7
0
R/W
BD6
R/W
22
0
6
0
R/W
BD5
R/W
21
0
5
0
R/W
R/W
BD4
20
0
4
0
R/W
R/W
BD3
19
0
3
0
R/W
R/W
BD2
18
0
2
0
R/W
R/W
BD1
17
0
1
0
R/W
R/W
BD0
16
0
0
0