R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 818

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 18 Serial Sound Interface (SSI)
18.3.3
SSITDR is a 32-bit register that stores data to be transmitted.
Data written to this register is transferred to the shift register upon transmission request. If the data
word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit
in SSICR. The data in the buffer can be accessed by reading this register.
SSITDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
18.3.4
SSIRDR is a 32-bit register that stores receive messages.
Data in this register is transferred from the shift register each time data word is received. If the
data word length is less than 32 bits, the alignment is determined by the setting of the PDTA
control bit in SSICR.
SSIRDR is initialized to H'00000000 by a power-on reset or in deep standby mode.
Rev. 2.00 Sep. 07, 2007 Page 786 of 1312
REJ09B0320-0200
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Transmit Data Register (SSITDR)
Receive Data Register (SSIRDR)
R/W
R/W
31
15
31
15
0
0
R
R
0
0
R/W
R/W
30
14
30
14
0
0
R
R
0
0
R/W
R/W
29
13
29
13
0
0
R
R
0
0
R/W
R/W
28
12
28
12
0
0
R
R
0
0
R/W
R/W
27
11
27
11
0
0
R
R
0
0
R/W
R/W
26
10
26
10
0
0
R
R
0
0
R/W
R/W
25
25
R
R
0
9
0
0
9
0
R/W
R/W
24
24
R
R
0
8
0
0
8
0
R/W
R/W
23
23
R
R
0
7
0
0
0
7
R/W
R/W
22
22
R
R
0
6
0
0
6
0
R/W
R/W
21
21
R
R
0
5
0
0
5
0
R/W
R/W
20
20
R
R
0
4
0
0
4
0
R/W
R/W
19
19
R
R
0
3
0
0
3
0
R/W
R/W
18
18
R
R
0
2
0
0
2
0
R/W
R/W
17
17
R
R
0
1
0
0
1
0
R/W
R/W
16
16
R
R
0
0
0
0
0
0