R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 984

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.1
CROMEN enables subcode processing and CD-ROM decoding, and stops CD-ROM decoding
forcibly.
Rev. 2.00 Sep. 07, 2007 Page 952 of 1312
REJ09B0320-0200
Bit
7
6
5
4 to 0
Bit Name
SUBC_EN
CROM_EN
CROM_STP 0

ROM-DEC Enable Control Register (CROMEN)
Initial value:
Initial
Value
0
0
All 0
R/W:
Bit:
SUBC_
R/W
EN
7
0
R/W
R/W
R/W
R/W
R/W
CROM_
R/W
EN
6
0
Description
Subcode Processing Enable
This bit should be set and cleared simultaneously with
CD-ROM Decoding Enable
When this bit is set to 1, CD-ROM decoding starts after
detection of a valid sync code. When the bit is cleared
to 0, decoding stops on completion of the processing for
the sector currently being decoded.
This bit is automatically cleared when the automatic
decode-stopping function woks or when CROM_STP =
1.
Forcible Stop of CD-ROM Decoding
When this bit is set to 1, CD-ROM decoding is stopped
immediately and the SUBC_EN and CROM_EN bits are
automatically reset to 0. Before decoding can resume,
this bit must be cleared to 0.
Reserved
These bits are always read as 0.The write value should
always be 0.
CROM_EN. It is automatically cleared when decoding
is automatically stopped due to an abnormal condition
or when CROM_STP = 1
CROM_
R/W
STP
5
0
R/W
—
4
0
R/W
—
3
0
R/W
—
2
0
R/W
—
1
0
R/W
—
0
0