R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 990

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.6
CROMCTL4 enables/disables buffering control at link block detection, specifies the information
indicated by the status register, and controls the ECC correction mode. The setting of this register
becomes valid at the sector-to-sector transition
Rev. 2.00 Sep. 07, 2007 Page 958 of 1312
REJ09B0320-0200
Bit
7
6
5
Bit Name
LINKOFF
LINK2

Decoding Option Setting Control Register (CROMCTL4)
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
LINK
OFF
R/W
7
0
R/W
R/W
R/W
R/W
LINK2
R/W
6
0
Description
Buffering Control at Link Block Detection
0: On
1: Off
When this bit is set to 1, buffering control is not
However, link-block detection processing does proceed,
Link Block Detection Condition
0: The block is regarded as a link block when either
1: The block is regarded as a link block when two out
When this bit is set to 1, buffering control for link blocks
is disabled (link blocks are processed as normal
sectors). The condition for setting of the LINK_ON bit in
CROMST5 is decoding of the link sector.
Reserved
This bit is always read as 0. The write value should
always be 0.
performed when a link block is detected. The link block
is processed as normal sectors.
and the results are reflected in the values of bits 3 to 0
in the CROMST5 register.
R/W
—
5
0
run-out 1 or 2 and both run-in 3 and 4 have been
detected.
of run-out 1 and 2 and "link" have been detected.
ER0
R/W
SEL
4
0
NO_
ECC
R/W
3
0
R/W
—
2
0
R/W
—
1
0
R/W
—
0
0