R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 296

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R5S72611

Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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Section 9 Bus State Controller (BSC)
(c)
Figures 9.21 and 9.22 show timing examples for byte accesses to the SDRAM with a 16-bit bus
width. In the SDRAM access, the DQM signal is asserted when data is masked.
Rev. 2.00 Sep. 07, 2007 Page 264 of 1312
REJ09B0320-0200
Byte Access Control by DQM
Figure 9.22 Byte Read Timing from SDRAM with 16-Bit Bus Width (Example)
Figure 9.21 Byte Write Timing to SDRAM with 16-Bit Bus Width (Example)
SDRAM command
SDRAM command
Data bus [15:8]
Data bus [15:8]
Data bus [7:0]
Data bus [7:0]
DQM1
DQM0
DQM1
DQM0
CKIO
CKIO
ACT
ACT
WR
RD
d0
PRA
DSL
High-Z
High-Z
Low level
Low level
PRA
d0

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