R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 913
R5S72611
Manufacturer Part Number
R5S72611
Description
32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.R5S72611.pdf
(1348 pages)
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Section 20 IEBus
Controller (IEB) [R5S72612] [R5S72613]
(b) Broadcast Bit
The broadcast bit is a bit to identify the type of communications: broadcast or normal.
When this bit is cleared to 0, it indicates broadcast communications. When it is set to 1, it
indicates normal communications. Broadcast communications includes group broadcast and
general broadcast, which are identified by a value of the slave address. (For details of the slave
address, see section 20.1.2 (3), Slave Address Field.)
Since multiple slave units are communications destination units, in the case of broadcast
communications, the acknowledge bit is not returned from each field described in (2) and below.
When more than one unit starts to transfer a communications frame with the same timing,
broadcast communications has priority over normal communications, and arbitration occurs.
(2)
Master Address Field
The master address field is a field for transmitting the unit address (master address) to other units.
The master address field is comprised of master address bits and a parity bit.
The master address consists of 12 bits and the MSB is output first.
When more than one unit start to transfer broadcast bits having the same value with the same
timing, arbitration is decided by the master address field.
In the master address field, self-output data and data on the bus are compared for every one-bit
transfer. If the self-output master address and data on the bus are different, the unit that loses
arbitration will stop its transfer and enter the receive state.
Since the IEBus is configured with wired AND, the unit having the smallest master address of the
units in arbitration (arbitration master) wins in arbitration.
Finally, only a single unit remains in the transfer state as a master unit after outputting a 12-bit
master address.
Next, this master unit outputs a parity bit*, defines the master address for other units, and then
enters the slave address field output state.
Note: * Since even parity is used, when the number of one bit in the master address is odd, the
parity bit is 1.
Rev. 2.00 Sep. 07, 2007 Page 881 of 1312
REJ09B0320-0200
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