R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 330

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10 Bus Monitor
10.1.4
SYCBESW controls the notification of various types of bus errors to the CPU.
Rev. 2.00 Sep. 07, 2007 Page 298 of 1312
REJ09B0320-0200
Bit
31
30
29
28
27 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bus Error Control Register (SYCBESW)
Bit Name
00CPEN
01CPEN

11CPEN

CPEN
R/W
31
15
00
—
R
0
0
CPEN
R/W
30
14
01
—
R
0
0
29
13
—
—
R
R
0
0
Initial
Value
0
0
0
0
All 0
CPEN
R/W
28
12
11
—
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R
R/W
R/W
R/W
26
10
—
—
R
R
0
0
Description
Bus Error Control (CPU → CPU)
This bit controls notification to the CPU when a bus
error is caused by the CPU.
0: Not notified
1: Notified
Bus Error Control (DMAC Destination Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC destination side.
0: Not notified
1: Notified
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Error Control (DMAC Source Side → CPU)
This bit controls notification to the CPU when a bus
error is caused by the DMAC source side.
0: Not notified
1: Notified
Reserved
These bits are always read as 0. The write value
should always be 0.
25
—
—
R
R
0
9
0
24
—
—
R
R
0
8
0
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
19
—
—
R
R
0
3
0
18
—
—
R
R
0
2
0
17
—
—
R
R
0
1
0
16
—
—
R
R
0
0
0