R5S72611 RENESAS [Renesas Technology Corp], R5S72611 Datasheet - Page 206

• Manufacturer Part Number: R5S72611
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 User Break Controller (UBC)
7.3.6
BRCR sets the following conditions:
1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle
2. Specifies the pulse width of the UBCTRG output when a break condition is satisfied.
BRCR is a 32-bit readable/writable register that has break condition match flags and bits for
setting other break conditions. For the condition match flags of bits 15 to 12, writing 1 is invalid
(previous values are retained) and writing 0 is only possible. To clear the flag, write 0 to the flag
bit to be cleared and 1 to all other flag bits. BRCR is initialized to H'00000000 by a power-on
reset and in deep standby, but retains its previous value by a manual reset or in software standby
mode or sleep mode.
Rev. 2.00 Sep. 07, 2007 Page 174 of 1312
REJ09B0320-0200
Bit
31 to 18
17, 16
Initial value:
Initial value:
is set before or after instruction execution.
R/W:
R/W:
Bit:
Bit:
Break Control Register (BRCR)
SCMFC
R/W
Bit Name

CKS[1:0]
31

15
R
0
0
0
SCMFC
R/W
30

14
R
0
0
1
SCMFD
R/W
29

13
R
0
0
0
Initial
Value
All 0
00
SCMFD
R/W
28

12
R
0
0
1
27

11

R
R
0
0
R/W
R
R/W
26

10

R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Select
Specifies the pulse width output to the UBCTRG pin
when a break condition is satisfied.
00: Pulse width of UBCTRG is one bus clock cycle
01: Pulse width of UBCTRG is two bus clock cycles
10: Pulse width of UBCTRG is four bus clock cycles
11: Pulse width of UBCTRG is eight bus clock cycles
25


R
R
0
9
0
24


R
R
0
8
0
23


R
R
0
7
0
PCB1 PCB0
R/W
22

R
0
6
0
R/W
21

R
0
5
0
20


R
R
0
4
0
19


R
R
0
3
0
18


R
R
0
2
0
R/W
17

R
CKS[1:0]
0
1
0
R/W
16

R
0
0
0