ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet
ORSPI4-2FTE1036I
Specifications of ORSPI4-2FTE1036I
Related parts for ORSPI4-2FTE1036I
ORSPI4-2FTE1036I Summary of contents
Page 1
... May 2009 Lattice Semiconductor has developed a next-generation FPSC targeted at high-speed data transmission. Built on the Series 4 reconfigurable embedded System-on-a-Chip (SoC) architecture, the ORSPI4 FPSC contains two SPI4.2 interface blocks, a high-speed Memory Controller, four channels of 0.6-3.7 Gbits/s SERDES with 8b/10b encoding and decoding and over 600K programmable system gates all on a single chip. ...
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... EBR usage and 2 PLL's. Maximum System Gates assumes 80% of the PFU's are for logic, 20% are used for PFU RAM, with 80% EBR usage and 4 PLL's. The ORSPI4 device is offered in two packages: 1036 ftSBGA and 1156 fpBGA. The 1036 package offers 498 FPGA User I/Os while the 1156 package offers 356 FPGA User I/Os. Additionally, the SERDES option is not available on the 1156 package. ...
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... Lattice Semiconductor ORSPI4 Overview The ORSPI4 FPSC provides two SPI4.2 interface blocks, a Memory Controller and a 4-channel SERDES block, combined with FPGA logic. Based on the 1.5 V OR4E06 ORCA FPGA, it has array of Programmable Logic Cells (PLCs). The embedded core is attached to the right side of the device, as shown below, and is inte- grated directly into the FPGA array. A top level diagram of the basic chip confi ...
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... The System Packet Interface Level 4, Phase 2 (SPI4) was defined by the Optical Internetworking Forum (OIF interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applica- tions requiring Gbit/s aggregate bandwidth. The system level model for the SPI4 interface is shown in Fig- ure 2. ORCA ORSPI4 Data Sheet 4 ...
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... Link Layer and Physical Layer functionality is not often seen in actual implementations. The ORSPI4 FPSC SPI4 blocks implement the basic functions defined in the standard and also implements addi- tional options, as suggested in the standard, to configure parameters such as maximum burst size, calendar length, length of training sequence, etc. As required by the specifi ...
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... The internal calendar and Transmit and Receive Status FIFOs have been sized so that applications with larger numbers of ports can be supported. The ORSPI4 has been designed to support up to 256 ports, the maximum specified in the SPI4 specification. ...
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... Mixed mode: One 64-bit (two banks become a single aggregation) and two banks are separate and accessed independently • Training pattern generation – User controlled “alpha” repetitions of training pattern in TX_DATA_MAX_T intervals – Automatic generation of training pattern during loss of synchronization ORCA ORSPI4 Data Sheet 7 ...
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... SPI4 Status Reporting Capabilities: – Status information is reported through status registers. – Most conditions can also cause an alarm (interrupt generated – DIP-4, DIP-2 errors – Deskew error from high-speed RX side – DPRAM Virtual FIFO overruns ORCA ORSPI4 Data Sheet ® -644 8 ...
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... Lattice Semiconductor Figure 3. ORSPI4 SPI4 Interface Block - Top Level Functional Partitioning Transmit Transmit Status Read Control Calendar Transmit Buffers 32, 64, Transmit Data 128 Write Transmit Control Control FIFO_FULL Receive Receive Status Transmit Buffers Address Map Receive Buffers Read Data 128 Receive ...
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... At the FPGA interface, processing will be done slightly differently, depending upon the mode the user requires. Each mode is discussed below. • Embedded memory mode - This mode is used when the ORSPI4 is interfacing to asynchronous FPGA inter- faces, such as POS-PHY Level 3, 1GbE, Utopia Level 3, etc. and storing the data in the virtual DPRAM FIFOs. ...
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... The Transmit Status Protocol (S4TSP) block provides the interface to the SPI4 Transmit Status interfaces. These signals can be either LVDS or LVCMOS buffers. The S4TSP block is responsible for the following functions: • FIFO Status Decoding and Buffering. • Framing using the status framing pattern. • DIP-2 checking of incoming status information. ORCA ORSPI4 Data Sheet 11 ...
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... At any time, the user can poll the status of a FIFO within a DPRAM bank by providing just the read address with- out a valid read enable. • A FIFO empty flag is generated by the read control logic to the FPGA. This empty flag can be programmed to indicate truly empty or < 1/4 full (1/4 full - 1). ORCA ORSPI4 Data Sheet 12 ...
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... DIP-2 parity bits. DIP-2 parity is then checked at the transmit status interface. • Eight-bit counters are provided for counting DIP-4 and DIP-2 errors. • Deskew error reporting for high-speed RX side dynamic alignment. This can cause an alarm. • DPRAM FIFO overrun reporting. These can cause an alarm. ORCA ORSPI4 Data Sheet 13 ...
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... Additional high-speed Memory Controller can be implemented in FPGA gates if required. SERDES Logic Block - Overview The SERDES logic block in of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and four Seri- alizer/Deserializer (SERDES) macrocells to support four channels of 8b/10b ( IEEE 802.3.2002) encoded serial links ...
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... The MUX/DEMUX logic converts the data format for the high-speed serial links to a wide, low-speed format for crossing the CORE/FPGA interface. The intermediate interface to the SERDES macrocell runs at 1/10th the bit SERDES w/ BYTE- CLOCK/DATA 8b/10b WIDE RECOVERY DECODER/ENCODER DATA 4:1 MUX/1:4 DEMUX 15 ORCA ORSPI4 Data Sheet 0.6 Gbits/s TO 3.7 Gbits/s DATA 4 FULL- DUPLEX CML SERIAL I/Os CHANNELS 0.6 Gbits ...
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... FPGA logic. Multi-Channel Alignment FIFOs In the ORSPI4 SERDES block, the four incoming data channels can be independent of each other or can be syn- chronized in several ways. Two channels within a SERDES block can be aligned together; channels A and B and/or channels C and D. Finally, four channels in a SERDES block can be aligned together to form a communication channel with a bandwidth of 10 Gbits/s ...
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... ORSPI4 FPGA Logic Overview The following sections provide a brief overview of the main architectural features of the ORSPI4 FPGA logic. For more detailed information, please refer to the ORCA Series 4 FPGA Data Sheet which can be found under the “Products” folder on the Lattice Semiconductor main Web site: www.latticesemi.com. The ORCA Series 4 FPGA Data Sheet provides detailed information required for designing with the ORSPI4 device ...
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... Large blocks of 512 x 18 quad-port RAM complement the existing distributed PFU memory. The RAM blocks can be used to implement RAM, ROM, FIFO, multiplier, and CAM. Some of the other system-level functions include the MPI, PLLs, and the Embedded System Bus (ESB). ORCA ORSPI4 Data Sheet 18 ...
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... New 200 MHz embedded quad-port RAM blocks, 2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be configured as: – 1—512 x 18 (quad-port, two read/two write) with optional built in arbitration. ORCA ORSPI4 Data Sheet 19 ...
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... New 2x/4x uplink and downlink I/O capabilities interface high-speed external I/Os to reduced speed internal logic. • Meets Universal Test and Operations PHY Interface for ATM (UTOPIA) levels 1, 2, and 3; as well as POS-PHY3. ORCA ORSPI4 Data Sheet ® processor) facilitates communication among 20 ...
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... Both local and global signals utilize high-speed buffered and non-buffered routes. One PLC segmented (x1), six PLC segmented (x6), and bused half chip (xHL) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. ORCA ORSPI4 Data Sheet 21 ...
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... JTAG configuration modes). Phase-Locked Loops The ORSPI4 provides 4 programmable PLLs accessible through clock routing in the FPGA array. There are two standard programmable PLLs (PPLL) and 2 high-speed programmable PLLs (HPPLL) available in the ORSPI4. The two PPLLs are capable of manipulating and conditioning clock outputs from 15 MHz to 200 MHz. The two HPPLLs are capable of manipulating and conditioning clock outputs from 60 MHz to 420 MHz ...
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... ORSPI4 to work in an independent system without an external microprocessor interface. ORSPI4 Package Options The ORSPI4 FPSC is available in two package options: a 1036 ftSBGA and a 1156 fpBGA. The 1036 pin package provides an OR4E06 FPGA array (16,192 LEs, 148 Kbits of Embedded Block RAM), 498 FPGA user I/Os, two SPI4 interfaces (or one SPI4 interface and a quad high-speed SERDES interface), and a high-speed QDRII SRAM Controller ...
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... Byte 3 Byte 2 Byte 4 x (set to zeros) 7 Byte 0 Byte 1 Byte 3 Byte 2 Byte 4 x (set to zeros) Word 1 Word BE1 BE2 Clock 2 Clock 3 24 ORCA ORSPI4 Data Sheet 0 0 Word BE3 Clock 4 ...
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... Byte 0 Byte 1Byte 2 Byte 3 Word 2 Clock 3 Time SPI[A,B]_TX64_DATA_j[63: Byte 0 Byte 1Byte 2 Byte 3 Word 1 Clock 2 Time 25 ORCA ORSPI4 Data Sheet FPGA DPRAM 127 Byte 0 Byte 1 Byte 2 Byte 3 Word 3 Clock 4 Byte 0 is the SOP FPGA ...
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... Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 SPI[A,B]_TX128_SOP SPI[A,B]_RX128_SOP SPI[A,B]_TX128_DATA[127:0] or SPI[A,B]_RX128_DATA[127: Byte 8 Byte 9 Byte 10 Byte 11 Word 0 Clock 1 Time 26 ORCA ORSPI4 Data Sheet DPRAM FPGA 127 Byte12 Byte 13 Byte 14 Byte Word 0 ...
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... SPI4 Transmit I/O Interface (TDO) • SPI4 Transmit Status Logic (TSP) – SPI4 Transmit Status Interface (TSI) – SPI4 Transmit Status Protocol (TSP) These blocks will be described in detail in the following sections. The ORSPI4 Transmit functional block diagram is shown in Figure 10. . ORCA ORSPI4 Data Sheet ...
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... Lattice Semiconductor Figure 10. ORSPI4 Transmit Functional Block Diagram k = TX32, TX64 or TX128 SPI[A,B]_k_DATA_j, BEj SPI[A,B]_k_SOPj, ERRj SPI[A,B]_k_ADDRj SPI[A,B]_k_PORT_j SPI[A,B]_k_WE_j SPI[A,B]_k_WD_CNT_RST_j SPI[A,B]_k_LINK_DIS_j SPI[A,B]_k_FIFO_FULL_j SPI[A,B]_k_CLK_j SPI[A,B]_k_PORT_ID SPI[A,B]_k_PORT_ID SPI[A,B]_k_STAT SPI[A,B]_k_BURST_VAL ...
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... TX Calendar Control Logic, where internal tables are updated accordingly to provide proper port servicing. ORSPI4 Transmit FPGA/Embedded Core Interface Description The FPGA I/O interface to the ORSPI4 logic supports several interface features and varying interface characteris- tics, depending upon the configured mode of operation. The modes are referred to as 'aggregation modes' due to the nature of the aggregation of data busses for the different modes of operation ...
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... Core →FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_0[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the con- figured fill level within the partition. 30 ORCA ORSPI4 Data Sheet Description ...
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... Core →FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_1[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the con- figured fill level within the partition. 31 ORCA ORSPI4 Data Sheet Description ...
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... Core →FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_3[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the con- figured fill level within the partition. 32 ORCA ORSPI4 Data Sheet Description ...
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... Core →FPGA FIFO full status. The status is given in response to the assertion of any valid address on the SPIA_TX32_ADDR_3[2:0] bus. This signal will be asserted to a logic '1' when the current FIFO partition has crossed the con- figured fill level within the partition. 33 ORCA ORSPI4 Data Sheet Description ...
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... FPGA must be 200 MHz. FPGA → Core ‘0’ - Incoming ATSCLK is assumed to be edge-aligned with the data and centered to the data eye within the chip. ‘1’ - Incoming ATSCLK is assumed to be skewed with respect to the data off-chip. 34 ORCA ORSPI4 Data Sheet Description ...
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... FPGA → Core Line Write Termination indicator. This signal causes the FIFO write address pointer within the embedded core to increment to the next address location for the addressed partition. This signal can be used for custom applications as well as for diagnostic test functions. 35 ORCA ORSPI4 Data Sheet Description ...
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... FIFO partition. End of Packet indicator. A '1' indicates the end of packet for a particular FPGA → Core port. The EOP may be asserted on either write per address line within the FIFO partition. 36 ORCA ORSPI4 Data Sheet Description ...
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... When operating in 128-bit mode, each partition will be 4x FPGA → Core the depth of the corresponding partition in 32-bit mode. More than one port can be configured to share a virtual FIFO partition. FPGA → Core User Write data. A single write will complete an entire 128-bit line. 37 ORCA ORSPI4 Data Sheet Description Description ...
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... Start of Packet indicator. A '1' indicates the start of packet for a particular port. When operating in 128-bit mode, the SOP indicator must be asserted FPGA → Core coincident with the first line write to the FIFO partition in order to align the start of packet data with the SOP sideband signal. 38 ORCA ORSPI4 Data Sheet Description ...
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... FPGA must be 200 MHz. FPGA → Core ‘0’ - Incoming ATSCLK is assumed to be edge-aligned with the data and centered to the data eye within the chip. ‘1’ - Incoming ATSCLK is assumed to be skewed with respect to the data off-chip. 39 ORCA ORSPI4 Data Sheet Description ...
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... FPGA, the internal DPRAM pointer logic advances to the next valid address within partition range after every 4 writes when in 32-bit aggregation mode Partition Addr 'k' 0xF 0xF 0xF 0xF 0xF 0xF Port 3 40 ORCA ORSPI4 Data Sheet 0xF 0xC Port 3 ...
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... Port is permitted to be written to any single 128-bit location within the DPRAM partitions Partition Addr 'k' Addr 'k+1' 0xF 0xF 0xF 0xF 0xF 0xF Port 3 Port 7 Addr 'n' Addr 'm' 41 ORCA ORSPI4 Data Sheet Addr 'k' 0xF 0x8 0xF 0xF Port 3 'm+1' Addr 'n+1' ...
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... DPRAM line entry. The same interface logic in the FPGA can also be used as described in 32-bit mode, but the counter implemented in FPGA logic is simply a one-bit toggle FF Partition Addr 'k' 0xFF 0xFF 0xFF 0xFF 0xFF Port 3 Port 3 42 ORCA ORSPI4 Data Sheet 6 7 0xFE Port 3 ...
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... Figure 15 below shows the protocol required when operating in 128-bit aggregation mode. A single write from the FPGA fills an entire line within a FIFO partition Part. Addr 'k' Partition Addr 'k+4' 0xFF 0xFF 0xFF 0xFF 0xFF Port 7 Port 3 Addr 'n' Addr 'm' 43 ORCA ORSPI4 Data Sheet Part. Addr 'k' 0xFC 0xFF 0xC0 Port 3 'm+1' 'n+1' ...
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... Table 2, Table 3, and Table 4) from the FPGA. Table 5 shows the indexed partition based upon the configured DPRAM partitioning and aggregation mode Part. Addr 'k' Addr 'j' Partition Addr 'j+4' 0xFFFF 0xFFF8 0xFFFF 0xFFFF Port 3 Port 7 44 ORCA ORSPI4 Data Sheet 5 6 0xFFFF Port 2 ...
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... Upon removal of the Link Disable signal, ports from the enabled DPRAM will be serviced according to the configured Calendar sequence. The following is an example of the effect of asserting a Link Disable. For this example, assume the ORSPI4 is con- figured as follows: ...
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... Figure 17 shows how the port polling changes when a second bank is disabled. SPIB_TX32_LINK_DIS_2 is asserted to disable port 2. The port polling period with two ports disabled becomes 2 ports X 4 cycles/port + 4 extra cycles = 12 cycles ORCA ORSPI4 Data Sheet Here the signal ...
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... Configured Virtual FIFO DATA FIFO Depth Partitions (in Bytes 512 8 256 512 ORCA ORSPI4 Data Sheet Control FIFO Depth (in Bytes) 512 256 128 64 1K 512 256 128 2K 1K 512 256 ...
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... ORCA ORSPI4 Data Sheet Configuration ...
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... ORCA ORSPI4 Data Sheet Configuration ...
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... When the Transmit status receives excessive errors, the status block sends consecutive '11' patterns to the TDP. According to the SPI4 specification, the TDP will begin sending training patterns across the SPI4 link until the sta- tus error is remedied. ORCA ORSPI4 Data Sheet 50 ...
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... AMA, integrating transmit status update information into the servicing of ports according to the SPI4 specification, and providing port service information to the FPGA for traffic monitoring. To AMA BURST_VAL AMA_ID 8 TX CALENDAR PORT_ID 2 Control PORT_STAT Logic 4 51 ORCA ORSPI4 Data Sheet From External I/O TLSTAT ATSTAT TSI TSP TLSCLK ATSCLK ...
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... DPRAM FIFO partition. After reset this field defaults to a value of 4'h0. Transmit Port Seq Addr Calendar Main/ Port Desc Data Shadow Port Descriptor Memory CREDIT MB_EN M BURST_VAL 52 ORCA ORSPI4 Data Sheet 0 PORT_ID STATUS UPDATE PORT_STAT LOGIC 255 PORT_ID AMA STATUS BANK_ID PARTITION_ID ...
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... TDP block for processing. The TSP provides port status information to the Transmit Calendar logic along with the associated port number. The Calendar logic then updates the appropriate Port STAT field. The TSP block also sup- ports Hitless Bandwidth Provisioning as defined within Appendix G of the SPI4 specification. ORCA ORSPI4 Data Sheet 53 ...
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... For all combinations of aggregation, the values given above apply. • More than one port can be mapped to the same partition. Simply program the same PARTITION_ID and BANK_ID values in all the PDM port entries that share the same partition. ORCA ORSPI4 Data Sheet 54 ...
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... STARVING is received, transfers for up to Maxburst1 16-byte blocks may be sent to the corresponding port prior to the next status update. Internal to ORSPI4, the “16-byte blocks” term is also called BURST_VAL. Even though the Maxburst1 and Maxburst2 are global parameters for all the ports, each port has its own BURST_VAL parameter attached to it that the user must program in the Transmit Port Descriptor Memory (TXPDM). Every time the TX sta- tus is updated for a port, Maxburst1 or Maxburst2 values are loaded into the credits fi ...
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... The user must configure the 32-bit TX_DATA_MAX_T variable to indicate the number of clock cycles that should lapse between training sequence. A value of 0x00000000 disables training. By default training is disabled. START Tx NO YES STATUS UPDATE HUNGRY SATISFIED STATUS NO MB_EN STARVING YES Credits = Maxburst1 Credits = Maxburst2 Data Sent = BURST_VAL * 128 Bits Description: 56 ORCA ORSPI4 Data Sheet ...
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... The calendar length register TX_CAL_LEN_MAIN is set to 16 (address 30922 and 30923 in SPIA, 30A22 and 30A23 in SPIB). 8-Bit Port ID Port Bandwidth (Port Address) A1 STS-12 0x00 A2 STS-12 0x01 A3 STS-12 0x02 B1 STS-3 0x03 B2 STS-3 0x04 B3 STS-3 0x05 B4 STS-3 0x06 57 ORCA ORSPI4 Data Sheet ...
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... It is important to enable this feature in the receive device on the other end of the SPI4 link. If the receive device is a Lattice ORSPI4 device, this is done by setting RX_CAL_SW_EN bit (address 30916 in SPIA and 30A16 in SPIB) to ‘1’. This will cause the far-end receive status logic to insert the calendar select word after the framing pattern ...
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... Figure 21, Figure 22, and Figure 23 illustrate a BURST_VAL of 4, but are extendable to BURST_VAL values from 2 to 15. Note that BURST_VAL for each port is available on SPI[A,B]_k_BURST_VAL. This may be useful in cases where BURST_VAL has not been set to the same value for each port. ORCA ORSPI4 Data Sheet 59 ...
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... Within valid time to load portís transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port 60 ORCA ORSPI4 Data Sheet Minimum separation between repeating port numbers in Transmit Calendar = 4 for 32-bit mode to allow time to load Transmit FIFOs for data bursts of any length ...
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... Within valid time to load portís transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port 61 ORCA ORSPI4 Data Sheet Minimum separation between repeating port numbers in Transmit Calendar = 2 for 64-bit mode to allow time to load Transmit FIFOs for data bursts of any length ...
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... Port status is not SATISFIED and 3. Within valid time to load portís transmit FIFO as shown above then OK to load transmit FIFO with BURST_VAL of data for that port 62 ORCA ORSPI4 Data Sheet 128-bit mode allows for consecutive port polling for any value of BURST_VAL . . . Port 0 End of data ...
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... DUMMY WRITE EOP OK 63 ORCA ORSPI4 Data Sheet If EOP occurs in any write EXCEPT last write for a given BURST_VAL, must include 1 dummy write before terminating writes for the port Dummy Write: SPI[A,B]_TX128_ERR = 1 SPI[A,B]_TX128_EOP = 0 SPI[A,B]_TX128_BE[15:0] = 0xFFFF SPI[A,B]_TX128_DATA = Donít Care ...
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... DUMMY WRITE EOP OK EOP OK 64 ORCA ORSPI4 Data Sheet If EOP occurs in any write EXCEPT last two writes for a given BURST_VAL, must include 1 dummy write before terminating writes for the port Dummy Write: SPI[A,B]_TX64_ERR_j = 1 SPI[A,B]_TX64_EOP_j = 0 SPI[A,B]_TX64_BE_j(7:0) = 0xFF SPI[A,B]_TX64_DATA = Doní ...
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... EOP EOP EOP EOP ORCA ORSPI4 Data Sheet If EOP occurs in any write EXCEPT last four writes for a given BURST_VAL, must include 1 dummy write before terminating writes for the port Dummy Write: SPI[A,B]_TX32_ERR_j = 1 SPI[A,B]_TX32_EOP_j = 0 SPI[A,B]_TX32_BE_j(3:0) = 0xF SPI[A,B]_TX32_DATA = Donít Care ...
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... Fast propagation delays for the embedded core output status signals as well as the clock signal. With the given timing delays the FPGA logic can either immediately register the provided status information or, if required, implement some combinatorial logic function before registering the information. 4. Delay C Delay 1.36/ 0. ORCA ORSPI4 Data Sheet D1 Setup = 2.6 ns Hold = - 0.32 ns ...
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... Special Operating Modes Quarter-Rate Mode The ORSPI4 SPI4 TX interface is designed to operate at data rates much lower than 622 Mbps. Even though the OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ethernet, etc.). ...
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... These features, and the SPI4 data formats and initialization procedures are documented in separate sections since they involve both the transmit and receive paths. The major blocks associated with the ORSPI4 receiver are: • SPI4 Receive Logic - Data – ...
Page 69
... Lattice Semiconductor These blocks will be described in detail in the following sections. The ORSPI4 Receive functional block diagram is shown in Figure 29. Figure 29. ORSPI4 Receive Functional Block Diagram SPI[A,B]_k_DATA_j, BE_j SPI[A,B]_k_ CTL_j (32 and 64 only) SPI[A,B]_k_SOPj, EOPj, ERRj 3 [A,B]STOP_ON_EOPj SPI[A,B]_k_RD_j SPI[A,B]_k_CLK_j ...
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... FIFOs. The user can select a 32-bit, 64-bit or 128-bit wide FIFO interface depending on the FPGA design requirements. There are two SPI4 cores in the ORSPI4 device. They are referenced in the document as SPIA and SPIB respec- tively. ...
Page 71
... When this bit is set to ‘1’, the empty flag indicates that the FIFO is 1/4 full -1. FPGA → Core Timing control for handling end of packet. FPGA → Core FIFO read clock. FPGA → Core FIFO read enable. 71 ORCA ORSPI4 Data Sheet Description ...
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... Enables delay line circuit on the ARDCLK path. FPGA → Core These bits control the effective delay of the delay line circuit on the ARD- CLK path. Valid values are from 0-6. Core →FPGA Internal clock (ARDCLK/4) used to clock all receive status logic. 72 ORCA ORSPI4 Data Sheet Description ...
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... When this bit is set to ‘1’, the empty flag indicates that the FIFO is 1/4 full -1. FPGA → Core Timing control for handling end of packet. FPGA → Core FIFO read clock. FPGA → Core FIFO read enable. 73 ORCA ORSPI4 Data Sheet Description ...
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... Enables delay line circuit on the ARDCLK path. FPGA → Core These bits control the effective delay of the delay line circuit on the ARD- CLK path. Valid values are from 0-6. Core →FPGA Internal clock (ARDCLK/4) used to clock all receive status logic. 74 ORCA ORSPI4 Data Sheet Description ...
Page 75
... Enables delay line circuit on the ARDCLK path. FPGA → Core These bits control the effective delay of the delay line circuit on the ARD- CLK path. Valid values are from 0-6. Core →FPGA Internal clock (ARDCLK/4) used to clock all receive status logic. 75 ORCA ORSPI4 Data Sheet Description ...
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... SPI4 receive clock RDCLK. The ORSPI4 receive high-speed interface also supports static data capture as shown in Figure 30. As shown in the figure, the key difference that exists between the clock and data paths is the delay line in the clock path. The high- speed loopback works in both static and dynamic alignment modes ...
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... Selects FIFO 4 when DPRAM is configured to support 8 virtual FIFOs 101 Selects FIFO 5 when DPRAM is configured to support 8 virtual FIFOs 110 Selects FIFO 6 when DPRAM is configured to support 8 virtual FIFOs 111 Selects FIFO 7 when DPRAM is configured to support 8 virtual FIFOs ORCA ORSPI4 Data Sheet Description 77 ...
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... 512 ORCA ORSPI4 Data Sheet Valid Yes Yes Yes Yes Yes No No Control FIFO Depth (in Bytes) 512 256 128 64 1K 512 256 128 2K 1K 512 256 ...
Page 79
... ORCA ORSPI4 Data Sheet Configuration ...
Page 80
... To decode the physical memory information, this block accesses a user-configured Port Descriptor Memory (PDM) which is simply a look-up-table. The PDM is an embedded memory within the ORSPI4 core. There is one each for SPIA and SPIB cores. Since 256 ports can be supported by the device, the PDM has 256 locations. The user indexes this memory using the 8-bit SPI4 Port ID as the software write address into the embedded memory space 31000 - 310FF. For example, a software write into address 31000 confi ...
Page 81
... A single port or multiple ports can be assigned to a buffer by configuring the PDM. The user must, using FPGA logic, assure that data is read from the virtual FIFO using the same port sequencing that is expected ORCA ORSPI4 Data Sheet Software Write ...
Page 82
... If the user application supports more than 32 ports, multiple ports need to share a buffer or external memory can be used. The ORSPI4 core provides a QDR-II SRAM Memory Controller for additional buffering. The QDR-II SRAM memory was chosen owing to the wire-speed throughput that can be realized through dedicated write and read ports ...
Page 83
... Status frame creation SPI[A,B]_k_EX SPI[A,B]_k_ST fill 1 2 ⁄ ≥ T_STAT_EN AT[1: ORCA ORSPI4 Data Sheet SPI4 Status Encoding x SATISFIED “00” STARVING “01” HUNGRY “10” SATISFIED x STARVING x HUNGRY “11” Disabled link ...
Page 84
... Provides information on the buffer space for a port or traffic flow • Allows user to allocate bandwidth for a port or flow depending on the overall traffic characteristics. DESKEWED RX_CALENDAR_SW_EN = ‘1’ SYNC RESET RX_CALENDAR_SW_EN= “0” RESET CAL CAL_DONE 84 ORCA ORSPI4 Data Sheet SWITCH RX_CAL_LEN_MAIN/SHD, RX_CAL_M_MAIN/SHD ...
Page 85
... This will cause the far-end transmit status logic to detect the calendar select word after the framing pattern. 8-Bit Port ID Port Bandwidth (Port Address) A1 STS-12 0x00 A2 STS-12 0x01 A3 STS-12 0x02 B1 STS-3 0x03 B2 STS-3 0x04 B3 STS-3 0x05 B4 STS-3 0x06 85 ORCA ORSPI4 Data Sheet ...
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... ID is presented to the user as this is redundant. The ASTOP_ON_EOPj is RX Calendar Memory Contents (Port ID) Port Number 0x00 A1 0x01 A2 0x02 A3 0x03 B1 0x00 A1 0x01 A2 0x02 A3 0x04 B2 0x00 A1 0x01 A2 0x02 A3 0x05 B3 0x00 A1 0x01 A2 0x02 A3 0x06 B4 86 ORCA ORSPI4 Data Sheet ...
Page 87
... As shown in Figure 35, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until EOP occurs. However, the user is always required to use the ERR signal in conjunction with the EOP signal. Irrespective of the ERR signal being asserted, the core always transmits the entire packet ...
Page 88
... ORCA ORSPI4 Data Sheet FIFO size = 16 locations. …. …. FIFO address changes during last 4-word burst of address n p Empty flag is low for FIFO Addressed by n, FIFO has three 4-word bursts of data …. ...
Page 89
... ASTOP_ON_EOPj SPIA_RX32_BE_j[3: word 0 from pointer location in FIFO address word word word cycles after read enable ORCA ORSPI4 Data Sheet FIFO size = 16 locations. …. …. Idle cycles inserted ...
Page 90
... During these idle cycles, the byte enable bits are set to all ‘0’s indicating that the read data is not valid. After cycles after read enable ORCA ORSPI4 Data Sheet FIFO size = 16 locations. …. … ...
Page 91
... As shown in Figure 38, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal. ...
Page 92
... ASTOP_ON_EOPj SPIA_RX64_BE_j[7: word 0 from pointer location in FIFO address word cycles after read enable Port ID h01 hff hff hff 92 ORCA ORSPI4 Data Sheet FIFO size = 32 locations. …. …. Idle cycles inserted nb na hff h00 h00 hff nb hff ...
Page 93
... Figure 41 indicate a FIFO size of 64 locations. Each location contains a 128-bit word. Thus when cycles after read enable Port ID h01 hff hff hff FIFO address n 93 ORCA ORSPI4 Data Sheet FIFO size = 32 locations. …. … hff hff hff hff nb hff ...
Page 94
... As shown in Figure 41, the ERR signal indicates that the corresponding packet is in error. The ERR signal can be asserted by the ORSPI4 core several clock cycles before EOP and remains asserted until the clock cycle when EOP is asserted. However, the user is always required to use the ERR signal in conjunction with the EOP signal. ...
Page 95
... SPIA_RX128_CLK 1 2 SPIA_RX128_RD SPIA_RX128_ADDR n SPIA_RX128_FIFO_EMPTY SPIA_RX128_DATA SPIA_RX128_SOP SPIA_RX128_EOP SPIA_RX128_ERR ASTOP_ON_EOP SPIA_RX128_BE cycles after read enable hffff hffff hffff hffff 95 ORCA ORSPI4 Data Sheet FIFO size = 64 locations. …. …. Idle cycles inserted D4 D0 hffff h0000 h0000 hffff D1 hffff ...
Page 96
... Special Operating Modes Static Capture Mode The ORSPI4 receiver supports both dynamic and static capture of data at the high-speed SPI4 interface. All the operating modes (32-bit, 64-bit and 128-bit) are independent of the type of data capture. They can operate in either static or dynamic capture mode. The choice of static vs. dynamic alignment depends on the SPI4 data rates. The static data capture is valid in the frequency range 400-700 Mbps ...
Page 97
... Lattice Semiconductor The ORSPI4 SPI4 RX interface is also designed to operate at data rates much lower than 622 Mbps. Even though the OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ether- net, etc.). To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE (Address 30915 in SPIA and 30A15 in SPIB) to ‘ ...
Page 98
... SPI-4 port clock. 2. Configure the appropriate ORSPI4 register as shown in Table 25. Note that either choice of LVTTL or LVDS for status buffer is acceptable for far end loopback, although the choice will affect the status port timing. Also note that bits 6 and 7 (TX_FORCE_DIP4_ERR and RX_FORCE_DIP2_ERR) do not affect the operation of far end loopback ...
Page 99
... RDAT inputs and RSTAT to TSTAT status inputs just before I/O. Enables near-end parallel loopback from TDP to RDP blocks and RSP to TSP blocks bypassing the high-speed SPI4 interface logic blocks. Must enable SPI4_LOOPBK_HS for this to work. 99 ORCA ORSPI4 Data Sheet Quarter Rate Far Static Dynamic End Far End ...
Page 100
... DPRAMs TDP b + associated logic Port write TSP Sequencer RX DPRAMs RDP + associated clk logic Port Status RSP Sequencer clk 100 ORCA ORSPI4 Data Sheet SPI4 I/F 128-bit TDAT[15:0] data+ctl TCTL TDO TDCLK TREFCLK TSTAT[1:0] clk TSCLK 128-bit RDAT[15:0] data+ctl RCTL RDI RDCLK RSTAT[1:0] ...
Page 101
... SPIA_TXk_CLK_j: Write clocks from FPGA to each of the four asynchronous DPRAMs 32 128) ATREFCLK_F: Clock output to the FPGA. Its frequency is the same as ATREFCLK used to clock the status outputs to the FPGA, namely SPIA_TXk_PORT_ID, SPIA_TXk_STAT and SPIA_TXk_BURST_VAL. ORCA ORSPI4 Data Sheet ATREFCLK SPIA TX Core ATDCLKP ...
Page 102
... SPIA_RXk_PSS_CLK: Write clocks from FPGA to the receive status RAM. The ARLSCLK_F clock can be used to source this clock as shown by dotted lines in the figure. ARSCLK[P,N]: LVDS receive status outputs. External pads. RSCLKA: 3.3 V LVTTL receive status output. External pads. ORCA ORSPI4 Data Sheet ARDCLKP SPIA RX Core ARDCLKN ...
Page 103
... Lattice Semiconductor SERDES Functional Description The SERDES portion of the ORSPI4 contains four Clock and Data Recovery (CDR) macrocells and Serial- ize/Deserialize (SERDES) blocks and supports 8b/10b (IEEE 802.3.2002) encoded serial links intended for high-speed serial backplane data transmission. Figure 47 shows the SERDES top level block diagram and the basic data fl ...
Page 104
... TSYS_CLK_x Core →FPGA TCK78 Receive Path Signals Core →FPGA MRWDx[39:0] Core →FPGA RWCKx Input ( Output (O) from Core Transmit low-speed clock to the FPGA—SERDES Quad Receive data—Channel x (see Table 35). Low-speed receive clock—Channel x. 104 ORCA ORSPI4 Data Sheet Signal Description ...
Page 105
... Logic Common to Quad Receive Channel A 2:1 MUX Link State (x40) Machine Multi - Channel DEMUX RX SER- Alignment Block DES Block Block Transmit Channel A Interface and TX SERDES MUX Block Block Channel B Channel C Channel D 105 ORCA ORSPI4 Data Sheet REFCLK[P:N] 2 HDIN[P:N]_A 2 Backplane Serial Links HDOUT[P:N] ...
Page 106
... The recovered data is aligned on a 10-bit boundary by detecting and aligning to special characters in the incoming data stream. Data is word-aligned using the comma (/K/) character. A comma character is a special character that contains a unique pattern (0011111 or its complement 1100000) in the 10-bit space that makes it useful for delim- ORCA ORSPI4 Data Sheet 106 ...
Page 107
... Multiplexer • CML Output Buffer Detailed descriptions of the logic blocks are given in following sections. Detailed descriptions of transmit clock dis- tribution, including the transmit PLL are given in later sections of this data sheet. ORCA ORSPI4 Data Sheet Encoded Word (–) K Control abcdei fghj ...
Page 108
... STBD_x[9] Force-ve disparity ÷ PLL STBC311_x 4 312.5 MHz Logic Common to Quad To other 3 From other 3 { channels channels From Control Register 108 ORCA ORSPI4 Data Sheet Backplane Serial Link TX SERDES Block HDOUTP_x 10:1 CML MUX Buffer with Pre- HDOUTN_x emphasis PRBS Gen. REFCLKP CML ...
Page 109
... LATENCY = 5 STBC311x CLOCKS 109 ORCA ORSPI4 Data Sheet 10-bit wide data ...
Page 110
... Applying too much preemphasis when it is not required, for example when driving a short backplane path, will also degrade the data eye opening at the receiver. In the ORSPI4 the degree of transmit preemphasis can be pro- grammed with a two-bit control from the microprocessor interface as shown in Table 28. The high-pass transfer function of the preemphasis circuit is given by the following equation, where the value of “ ...
Page 111
... MHz 2 Clocks XAUI State DEMUX Machine Block Logic Common to Quad To other 3 From other 3 { channels channels From Control Register 111 ORCA ORSPI4 Data Sheet Note: x= [A, ..., [1, 2] HDINP_x 1:10 Byte CML Align DEMUX Buffer (with HDIN_x CDR Backplane PLL PRBS Checker Serial ...
Page 112
... Lattice Semiconductor Synchronization The ORSPI4 SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each level builds upon the previous, providing first bit, then byte (character), then channel (32-bit word), and finally multi- channel alignment. Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi- tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data ...
Page 113
... DOWDALGN_x bit must be toggled to force resynchronization. EMBEDDED CORE ..... LATENCY = APPROX 23 CLOCKS ..... 113 ORCA ORSPI4 Data Sheet ..... Z ..... ..... ...
Page 114
... In the event of any such code violation, the machine would reset itself to the 114 ORCA ORSPI4 Data Sheet 40-bit 7-0 ...
Page 115
... SERDES byte aligner the user’s responsibility to control the byte aligner through software access of register map address 30800. LINK SYNCHRONIZATION ACHIEVED (WDSYNC = 1) 1VW LOSS OF SYNCHRONIZATION (WDSYNC_X = 0) OS 115 ORCA ORSPI4 Data Sheet 1VW 1VW LOS = 1 e ...
Page 116
... Indication that a valid code-group with the correct running disparity has been received. cg_bad Indication that an invalid code-group has been received. no_comma Indication that comma timer has expired. The timer is initialized upon receipt of a comma. ORCA ORSPI4 Data Sheet Description Description 116 ...
Page 117
... Reference Clock Requirements There is one pair of SERDES reference clock inputs on the ORSPI4. The differential reference clock is distributed to all channels in the block. Each channel has a differential buffer to isolate the clock from the other channels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input. The input reference clock directly impacts the transmit data eye, so the clock should have low jitter ...
Page 118
... RSYS_CLK_2 TSYS_CLK_D REFCLKP, REFCLKN: These are the differential reference clocks provided to the ORSPI4 device as described earlier. They are used as the reference clock for both TX and RX paths. For operation of the serial links at 3.125 Gbits/s, the reference clocks will frequency of 156.25 MHz. ...
Page 119
... TCK78[A: B] and RCK78[A:B] Clocks 60 MHz 15 MHz 100 MHz 25 MHz 125 MHz 31.25 MHz 100 MHz 50 MHz 125 MHz 62.5 MHz 156 MHz 78 MHz 185 MHz 92.5 MHz 119 ORCA ORSPI4 Data Sheet Rate of Channel Selected as Clock Source Half Half Half Full Full Full Full ...
Page 120
... Table 32. Table 32. TCK78 Source Selection Recommended Transmit Clock Distribution for the ORSPI4 As an example of the recommended clock distribution approach, TSYS_CLK_[A:D] can be sourced by TCK78 as shown in Figure 58 if the transmit line rate are common for all four channels in a quad. ...
Page 121
... TCK78 Common Logic Channel A Channel B Channel C Channel D RCKSEL0 RCKSEL1 Clock Source 0 0 Channel Channel Channel Channel C 121 ORCA ORSPI4 Data Sheet 2 REFCLK[P:N] 100 MHz Two Channels of 2.0 Gbits/s (Full-Rate) Outgoing Serial Data Two Channels of 1.0 Gbits/s (Half-Rate) Outgoing Serial Data ...
Page 122
... Channel C RWCKD Channel D RCK78 Common Logic RWCKA Channel A RWCKB Channel B RWCKC Channel C RWCKD Channel D 122 ORCA ORSPI4 Data Sheet 2 REFCLK[P:N] 156.25 MHz Four Channels of 3.125 Gbits/s Incoming Serial Data 2 REFCLK[P:N] 100 MHz Two Channels of 2.0 Gbits/s (Full-Rate) Incoming Serial Data Two Channels of 1 ...
Page 123
... FIFO-read-address to the middle of the FIFO, at the first assertion of RALIGN[3]_x after reset or after the resync command. The ORSPI4 has a total of four SERDES channels. The incoming data of these channels can be synchronized in several ways or can be independent of one another. Two SERDES channels can be aligned together. Channel A and B and/or channel C and D can form a pair as shown in Figure 62 ...
Page 124
... CV_A2, code violation, byte 2 K_CTRL for byte 2 bit 7 of byte 2 bit 6 of byte 2 124 ORCA ORSPI4 Data Sheet ...
Page 125
... The code violation signals will only be valid if the corresponding CV_SELx = “1”. (If 8b10bR=0, CV_SEL should also be zero. The CV_x_OR signals are obtained by ORing four code violation signals from the 1:4 DEMUX block. These are primarily indicators of received signal quality, since a single code violation will not force a loss of sync ORCA ORSPI4 Data Sheet 8b10bR=1 NOCHALGN[A:B]=1 ...
Page 126
... The exact number of clock cycles that the data is delayed depends on the skew between the incoming data for the different channels. Multi-Channel Alignment Clocking Strategies for the ORSPI4 The data on the four channels SERDES can be independent of each other or can be synchronized in several ways. ...
Page 127
... FMPU_RESYNC4 for quad [A:D] • FMPU_RESYNC2_1 for twin channel [A:B] Common Logic Channel A Channel B Channel C Channel D Register Bits Mode 00 No multi-channel alignment 10 Twin channel alignment 01 Quad channel alignment 127 ORCA ORSPI4 Data Sheet 2 REFCLK[P:N] 156.25 MHz Four Bidirectional Channels of 3.125 Gbits/s Serial Data ...
Page 128
... SERDES path can cause misalignment of data and OOS indica- tions without bringing the FC/XAUI state machine to a loss of sync state. A word alignment is achieved by writing a “0” and then a “1” to the appropriate DOWDALIGNx bits in registers 30810. ORCA ORSPI4 Data Sheet 128 ...
Page 129
... Relative to Data 1.5/0 FPGA 3.0ns Clock Tree TCK78 FPGA Embedded Core NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER 2.5 / 1.3 ns Delay Delay 1.1/ 0.18 ns SERDES_CLK ÷ MHz 311 MHZ 129 ORCA ORSPI4 Data Sheet D Setup = 1.5 ns Hold = - 0.8 ns ...
Page 130
... Clock: RSYS_CLK_1, RSYS_CLK_2 3.5/0 1.5/0 FPGA Embedded Core NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER 2.2 / 0.51ns (includes Clock Buffer Delay Relative to Data Delay 1.41/ 0.20 ns 130 ORCA ORSPI4 Data Sheet Total prop = 3 Delay ...
Page 131
... In general, loopback tests can be classified as “near end” or “far end”. In “near end” loopback (Figure 70(a)), data is generated and checked locally, i.e. by logic on, or connection of, test equipment to the same card as the FPSC. In “far end” loopback (Figure 70(b)), the generating and checking functions are performed remotely, either by test equipment or a remote system card. ORCA ORSPI4 Data Sheet 2 Delay 1 ...
Page 132
... Embedded Core SERDES Block DE 8B/10B CML SERDES MUX Buffer 8B/10B CML Buffer SERDES Parallel Loopback Connection 132 ORCA ORSPI4 Data Sheet Embedded Core HDIN[P:N]_xx CML 2 Buffer Non-Functional HDOUT[P:N]_xx CML 2 Buffer Active (to Eye Diagram Measurement or remote System Card) HDIN[P:N]_xx ...
Page 133
... The SERDES test mode requires that the SERDES block be selected instead of the SPIB block during the Module Generation phase of the ORSPI4 in ispLEVER . In addition, the TESTMD[1:0]N signals need to be set to “0” during SERDES characterization. ...
Page 134
... RBCO → PMID24 RBC1 → PMID25 LDOUT9 → PMID26 LDOUT8 → PMID 27 LDOUT7 → PMID28 LDOUT6 → PMID29 LDOUT5 → PMID30 LDOUT4 → PMID31 LDOUT3 → PMID32 LDOUT2 → PMID33 LDOUT1 → PMID34 LDOUT0 → PMID35 134 ORCA ORSPI4 Data Sheet Channel ...
Page 135
... Lattice Semiconductor Memory Controller Functional Description The ORSPI4 device includes a Memory Controller interface to an external second generation Quad Data Rate (QDRII) memory. This is provided for additional data buffering beyond the embedded DPRAMs. In this case, the embedded DPRAMs are used as clock-crossing domain FIFOs. The key requirement for this memory interface is the support of a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10 Gbits/s can be buffered ...
Page 136
... FIFO. Empty flag from MC Read data FIFO. Empty threshold is set by the MC_EMPTY_THRESHOLD register bits. Full flag from MC Read instruction FIFO. MC_RDFIFO_FULL HIGH indicates that only one more instruction can be written to the instruction FIFO. 136 ORCA ORSPI4 Data Sheet ...
Page 137
... FIFO. The write to location A4 cannot occur until the MC_WIFIFO_FULL flag is deasserted. The MC_WDFIFO_FULL flag remains low in this case since the full thresh- old for the data FIFO has not been reached Figure 73. ORSPI4 Memory Controller Interface to FPGA — Write Timing Diagram F_MC_WCLK F_MC_WDFIFO_WE ...
Page 138
... PMIA17, which is only used in 2-word mode, and thus must be connected to the corresponding QDRII SRAM address input that is only present on the 2-word device (if 2-word/4-word compatibility maintained). Flexibility in assigning these signals can be useful in optimizing the layout of this bus. ORCA ORSPI4 Data Sheet 138 ...
Page 139
... Lattice Semiconductor Figure 74. . ORSPI4 Memory Controller Interface to QDRII: 4-Word Burst Mode Figure 75 shows the timing of signals at the QDRII SRAM interface for two-word reads and writes. In this case, address data is sent on both the rising and falling edges of the positive clock signal. Write data is sent on the first rising edge of K before the write address and second data word are provided on the falling edge ...
Page 140
... MC by logic in the FPGA. The instruction fields are data length (number of cache lines to read) and address (for QDR memory). The read instruction and data word formats are shown in Figure 76 and Figure 77 respectively. ORCA ORSPI4 Data Sheet 140 ...
Page 141
... Lattice Semiconductor Figure 76. Read Data and Instruction Word Formats 31 Reserved (low) 71 Figure 77. ORSPI4 Memory Controller Interface to FPGA — Read Timing Diagram F_MC_RCLK F_MC_RIFIFO_WE F_MC_RI(23:18) D0*2 D1*1 F_MC_RI(17: MC_RIFIFO_FULL MC_RDFIFO_EMPTY F_MC_RDFIFO_RE MC_RD(71:0) The user can write/read instructions into the read instruction FIFO as long as the MC_RIFIFO_FULL flag is low. If this fl ...
Page 142
... For this example assumed that the clock from the FPGA logic to the Memory Controller (F_MC_WCLK) is synchronized to the K clock to the external memory. If these clocks are not synchronous, then the latency may vary. Figure 78. ORSPI4 QDR II Memory Controller – FPGA to External Memory Latency Example F_MC_WCLK = External Memory K Clock ...
Page 143
... Figure 79. Data: F_MC_WD[73:0], F_MC_WI[31:0], F_MC_RI[31:0] Clock: F_MC_WCLK 3.5/0 1.5/0.5 ns FPGA NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER 2.4/ 0. Delay Clock Buffer Delay Relative to Data C 1.1/ 0.74 ns Embedded Core 143 ORCA ORSPI4 Data Sheet FIFO Delay Setup= 1.6 ns Hold = 0.3 ns ...
Page 144
... Actual delay values are used by ispLEVER 2.4/ 0. Delay Clock Buffer Delay Relative to Data C 1.35/ 0.85 ns Embedded Core 2.7/ 0. Delay Clock Buffer Delay Relative to Data C 1.7/ 0.75 ns Embedded Core 144 ORCA ORSPI4 Data Sheet FIFO Delay Setup = 1.4 ns Setup = 1.4 ns Hold = 0.4 ns Hold = 0.4 ns FIFO Delay Setup= 2.8 ns Hold = 0.37 ns ...
Page 145
... NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER 2.5/ 0. Delay Clock Buffer Delay Relative to Data C 1.92/ 0.85 ns Embedded Core 1. Delay Clock Buffer Delay Relative to Data C 1.94/ 0.83 ns Embedded Core 145 ORCA ORSPI4 Data Sheet D Q Delay Setup= 2.0 ns Hold = 0.45 ns Total prop = 3 Delay ...
Page 146
... NOTE: Delays represent average max/min values, not absolute values Actual delay values are used by ispLEVER 1. Delay Clock Buffer Delay Relative to Data C 1.7/ 0.73 ns Embedded Core 0. Delay Clock Buffer Delay Relative to Data C 1.93/ 0.84 ns Embedded Core 146 ORCA ORSPI4 Data Sheet Total prop = 2 Delay Total prop = 3 Delay ...
Page 147
... Software Software for Configuration There are two ways to write to the ORSPI4 memory map either via MPI (Microprocessor Interface) or via UMI (User Master Interface) to the FPGA logic. Both the interfaces use the system bus to perform the transactions with the registers. The MPI is provided to talk to any Power PC microprocessor whereas UMI is used for any customer- defi ...
Page 148
... After the device is powered up, it resets itself with a Power-up reset, designed to trigger itself at power up. The first thing required by the ORSPI4 perform baseline process followed by training if dynamic alignment is chosen (SPI4_LOW_SPEED_DATA_SEL = ‘0’). This is required by the SPIA and SPIB high-speed receivers for internal ...
Page 149
... API to reprogram the TXPDM once the soft reset is pulsed. Soft reset may be required to pulse if because of any reason ORSPI4 loses its synchronization with another device. In that case “ORSPI4 baseline” procedure needs to be performed again by pulsing the soft reset. ...
Page 150
... MB_EN bit is set to ‘1’ which means that MAX-BURST1 and MAX-BURST2 both will be supported, otherwise only MAX-BURST1 will be used. • M bit is set to ‘1’ which means the port ID field programmed in the TX PDM is propagated to the FPGA on the ORCA ORSPI4 Data Sheet 150 ...
Page 151
... ORSPI4 has hand-shaken with another device properly. Delay-Taps in STATIC mode After all the configuration procedure is performed, there is a possibility of ORSPI4 experiencing DIP-4 errors and RX alignment status flag being high. This can be tackled using two FPGA/CORE interface signals called SPI_DATM_A and SPI_DLYTAP_A [2:0] ...
Page 152
... The FPGA Global Set Reset signal (GSR) can be made to reset the SPIA, SPIB and SERDES blocks of the ORSPI4 core. This can be done during the ORSPI4 Module/IP Generation phase of the ORSPI4 core in ispLEVER . During this phase, the “Disable GSR from resetting data path in FPSC Core” check button is left unchecked to enable GSR to reset these blocks ...
Page 153
... FPGA_RESET_FC performs the same function as HARD_RESET_FC. The difference is that FPGA inter- face signal instead of a configuration register bit. SYS_RST_N is a synchronous active low reset FPGA interface signal. This signal, when active, resets the read side of the multi-channel alignment FIFOs. ORCA ORSPI4 Data Sheet 153 ...
Page 154
... TRISTN This is an ORSPI4 EAC active low IO that globally tri-states all EAC IOs. Power-Up In addition to its RESET function, power-up also puts the ORSPI4 FPSC IO in tri-state until the chip is fully pow- ered up. Power Down When set low, the ORSPI4 FPSC “PDN” powers down the following: • ...
Page 155
... Each of the bits in the top-level interrupt status register 30B29 shown in Table 46 point to a specific functional block in the ORSPI4 device. Each of the bits in the SPIA or SPIB DPRAM top- level interrupt status register 30B2A is the collective OR of its associated lower-level interrupts. ...
Page 156
... SPI_A_1 Table 47 details the memory map for the FPSC portion of the ORSPI4 device. Addresses for the control registers for the FPGA portion of the device are detailed in the ORCA Series 4 datasheet. This table shows the databus oriented for the PPC interface. DB0 is the MSB, while DB7 is the LSB. If the user master interface is used to perform operations to the ASIC core then the databus must be used in the opposite notation, where DB7 is the MSB and DB0 is the LSB ...
Page 157
... Link State Machine Enable Bit, Channel x. When LINKSM_x = “1”, the receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre Channel link state machine is disabled. NOTE: LINKSM_x is ignored when XAUI_MODE_x= “1”. LINKSM_x = “0” on device reset. 157 ORCA ORSPI4 Data Sheet Description ...
Page 158
... Test Enable Control. When GTESTEN = “1”, the transmit and receive sec- tions of all four channels are placed in test mode. The GTESTEN bit over- rides the individual TESTEN_x bits. GTESTEN = “0” on device reset. 00 TestMode - See Test Mode section for settings 158 ORCA ORSPI4 Data Sheet Description ...
Page 159
... Controls use of XAUI link state machine in place of Fibre-Channel state machine. When XAUI_MODE= “1”, all four channels in the SERDES quad enable their XAUI link state machines. (LINKSM_x bits are ignored). XAUI_MODE= “0” on device reset. 159 ORCA ORSPI4 Data Sheet Description ...
Page 160
... XAUI Status Register. Status of XAUI link state machine for Channel x 00—No synchronization. 01—No comma (see XAUI state machine) and at least 1 cell value detected 10—Synchronization done. 11—Not used. XAUISTAT_x[0: device reset. 160 ORCA ORSPI4 Data Sheet Description ...
Page 161
... Shadow calendar length for the RX status frame of SPI4. Lower 8 bits. 00 Number of virtual FIFOs in RX DPRAM bank FIFO FIFOs FIFOs FIFOs Number of virtual FIFOs in RX DPRAM bank 1 Number of virtual FIFOs in RX DPRAM bank 2 Number of virtual FIFOs in RX DPRAM bank 3 161 ORCA ORSPI4 Data Sheet Description ...
Page 162
... This bit enables the status flag and the interrupt for the SPI4 core loss of RX alignment due to excess consecutive DIP4 errors. See RX_ALGN_OFF_STS in register 3091C[A], 3091C[B]. This bit enables the status flag and the interrupt for the SPI4 core TX status from having too many consecutive DIP2 errors. See TX_STATUS_LOF_STS 162 ORCA ORSPI4 Data Sheet Description ...
Page 163
... Detect the calendar select word after the frame sync pattern on the transmit status Mode control for managing the transmission of bursts when the DPRAM partition becomes empty in the middle of a burst. 0 =continue to try to access DPRAM for the remainder of burst abort the burst. 163 ORCA ORSPI4 Data Sheet Description ...
Page 164
... Length of main calendar sequence on the TX status frame. These are the most significant 2 bits of 10 total. Length of main calendar sequence on the TX status frame. These are the least significant 8 bits of 10 total. 00 Number of times the transmit shadow calendar sequence is repeated between insertions of framing pattern. 164 ORCA ORSPI4 Data Sheet Description ...
Page 165
... When this number is “0”, training sequences are disabled. 00 Maximum interval between training sequences on the transmit data inter- face. A 32-bit number is formed from 4 bytes organized as { and read left to right. When this number is "0", training sequences are disabled. 165 ORCA ORSPI4 Data Sheet Description ...
Page 166
... These bits clear when read, but will set immediately if the error condition persists. 00 Underrun status of bank 0 DPRAM FIFOs These are enabled by RX_DPRAM_FIFO_URRUN_INT_EN[0] (register 30912[A], 30A12[B]). These bits clear when read, but will set immediately if the condition persists. 166 ORCA ORSPI4 Data Sheet Description ...
Page 167
... Overrun status of bank 1 TX DPRAM FIFOs These are enabled by TX_DPRAM_FIFO_OVERRUN_INT_EN[1]. These bits clear when read, but will set immediately if the condition persists. This will happen when writing to the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high. 167 ORCA ORSPI4 Data Sheet Description ...
Page 168
... MC_RD_IFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write data FIFO overrun status flag MC_WR_DFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. Enable for Memory Controller write instruction FIFO overrun status flag MC_WR_IFIFO_OVERRUN_STS, and associated interrupt MEM_CTRL1_INT. 168 ORCA ORSPI4 Data Sheet Description ...
Page 169
... Status flag for read instruction FIFO overrun. Enabled by MC_RD_IFIFO_OVERRUN_INT_EN Status flag for write data FIFO overrun. Enabled by MC_WR_DFIFO_OVERRUN_INT_EN Status flag for write instruction FIFO overrun. Enabled by MC_WR_IFIFO_OVERRUN_INT_EN 00 Status flag for incoherent data and instruction words. Enabled by MC_ID_ERR_INT_EN. 169 ORCA ORSPI4 Data Sheet Description ...
Page 170
... Signals that an enabled interrupt has come from register 3091C. This is cleared when read and will only reassert when the underlying event goes away and comes back. 170 ORCA ORSPI4 Data Sheet Description ...
Page 171
... The following priority rules apply to the selection of which memory is read from. (1) 30917 bits take precedence over bits in the 30A17 register. (2) lower bit numbers take precedence over higher bit numbers within a reg- ister. 171 ORCA ORSPI4 Data Sheet Description ...
Page 172
... Power Supply Voltage with Respect to Ground SPI4 Voltages with respect to Ground Memory Controller Voltages with respect to Ground SERDES Supply Voltages FPGA Input Signal with Respect to Ground FPGA Signal Applied to High-impedance Output Maximum Package Body (Soldering) Temperature ORCA ORSPI4 Data Sheet Symbol Min. T -65 STG ...
Page 173
... DDH REF_1 0.64 REF_2 0.64 REF_3 0.64 REF_4 0.64 V 3.0 DDA_PLL V 1.425 DD_ANA V 1.425 DDGB V 1.425 DDIB V 1.425 DDOB IWMCTRL ss T – 173 ORCA ORSPI4 Data Sheet Max. Unit 3.6 V 3.6 V 1.575 V 1.575 V 1.575 V 1.575 V 1.575 V 1.575 V 0.87 V 0.87 V 0.87 V 0.87 V 3.6 V 1.575 V 1.575 V 1. ...
Page 174
... C, VDD15 = 1.575V, VDD33 = 3.6V, VDDIO = 3.6V, internal oscillator running, no output loads, inputs VDDIO or VSS. A Standby current is tested with the embedded core in a powered down state. Table 51. ORSPI4 Combined SPIA and SPIB Worst Case Power Table Parameter 450 MHz (900 Mbps) with Dynamic Alignment Frequency 112 ...
Page 175
... SERDES, MUX/DEMUX, Align FIFO and I/O (per channel) SERDES, MUX/DEMUX, Align FIFO and I/O (per channel) 8b/10b Encoder/Decoder (per channel) 1. With all channels operating, Temperature: -40 2. With ORSPI4 CML output buffers connected to ORSPI4 CML input buffers. Actual power dissipation can vary depending on the termination used. Operating Frequency 1 ...
Page 176
... GPD V IDTH 450 MHz V (+V ) – (–V ) HYST IDTHH IDTHL With build-in termination center-tapped Test Conditions Min. — 80 — 80 176 ORCA ORSPI4 Data Sheet Min. Typ. Max. Units † — — 1.475 V † 0.925 — — V † 0.25 — 0.45 V † 1.125* — ...
Page 177
... PAD PAD Any differential pair on pack- t age at 50% point of the tran- SKEW1 sition Ω differential impedance, as shown below. External resistors are not Center Tap External Device Pins 177 ORCA ORSPI4 Data Sheet 3pF Min. Typ. Max. 100 — 210 = 3.0 pF 100 — ...
Page 178
... Lattice Semiconductor SPI4 AC Timing Supported Data Rates The SPI4 interfaces (SPIA and SPIB) on the ORSPI4 device support the following data rates Table 58. Supported Data Rates Clock Frequency Data Rate (DDR) 500 -900 Mbps 250 - 450 MHz 500 -650 Mbps 250 - 325 MHz ...
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... Figure 92. SPI4.2 Receive Timing Points with Respect to Clock Edge Capture Edge (B) RDCLK RDAT Description and t which show the setup and hold requirements at the ORSPI4 179 ORCA ORSPI4 Data Sheet Min Max Units — ...
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... SPI_DLYTAP_A,B[2:0]=0 ORSPI4 Receive data hold with respect to clock capture edge SPI_DLYTAP_A,B[2:0]=1 ORSPI4 Receive data hold with respect to clock capture edge SPI_DLYTAP_A,B[2:0]=2 ORSPI4 Receive data hold with respect to clock capture edge SPI_DLYTAP_A,B[2:0]= ORSPI4 Receive data hold with respect to clock capture edge ...
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... Lattice Semiconductor The static timing budget for a data transfer between two ORSPI4 devices at a data rate of 650 Mbps in shown in Table 61. Table 61. Data Path Interface Timing Example for Static Alignment (ORSPI4 to ORSPI4) Description 1 Before reference point A Between reference points A and B After reference point B Note 1: ORSPI4 Transmit Specifi ...
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... Lattice Semiconductor The dynamic alignment timing budget for a data transfer between two ORSPI4 devices is shown in Table 62. Table 62. Data Path Parameters for Dynamic Alignment. Description Transmit clock jitter Transmit data jitter with respect to clock edge Receive clock jitter tolerance With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, 900 Mbit/s data rate with 112.5 Mhz REFCLK, REFCLK jitter -40º ...
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... Hold time for TSTAT with respect to TSCLK - LVDS Buffers (Reference point D) Note: This table compares the OIF Specification requirements vs. the ORSPI4 Specification. There is no OIF Specification for LVDS buffers. Figure 95. ORSPI4 Static Mode Status Signals Data Capture (Reference Point D) ...
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... LVTTL Buffers (Reference point Hold time for TSTAT with respect to TSCLK - LVDS Buffers (Reference point D) Note: This table compares the OIF Specification requirements vs. the ORSPI4 Specification. There is no OIF Specification for LVDS buffers. Capture Edge ( ...
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... Wavecrest SIA-3000 instrument used to measure one-sigma (rms) random jitter component value. This value is multiplied provide the peak-to-peak value that corresponds to a BER Total jitter measurement performed with Wavecrest SIA-3000 at a BER of 10 cations for a detailed discussion of jitter types included in this measurement. ORCA ORSPI4 Data Sheet Min. Typ. 50 ...
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... Input level min + (input peak to peak swing)/2 ≤ common mode input voltage ≤ input level max - (input peak to peak swing)/2 3. The ORSPI4 SERDES receiver performs four levels of synchronization on the incoming serial data stream, providing first bit, then byte (character), then channel (32-bit word), and finally optional multi-channel alignment as described in TN1025. The PLL Lock Time is the time required for the CDR PLL to lock to the transitions in the incoming high-speed serial data stream ...
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... The Clock and Data Recovery (CDR) portion of the ORSPI4 SERDES receiver has the ability to filter incoming sig- nal jitter that is below the clock recovery PLL bandwidth (about 3 MHz). The eye-mask specifications of Table 70 are for jitter frequencies above the PLL bandwidth of the CDR, which is a worst case condition. When jitter occurs at frequencies below the PLL bandwidth, the receiver jitter tolerance is signifi ...
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... The latency specified in the table is for data from the channel received first. Min. Typ. 60 -350 40 — — — 500 V 0.75 single-ended/2 250 — — 1 188 ORCA ORSPI4 Data Sheet Max. — 185 — 350 50 60 500 1000 500 1000 — 75 800 DDIB V 15 – ...
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... VIL 2 VOH IOH > Class 1 VOL IOL > VOH IOH > Class 2 VOL IOL > - 50% VDDH 2. VDDH - 400 mV. Min Typical -- 1.425 1.5 -- 0.64 0. 0.75 -- REFI + 100mV 0.85 -- -0.3 0.65 VDDH - 0.4 1 VDDH - 0.4 1 189 ORCA ORSPI4 Data Sheet Max Unit 1.575 V 0. VDDH + 0.3 V REFI -100 0 0.4 V ...
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... Signals PMID, HSTL-II PMIA, Output PMIWN, Buffer PMIRN & PMIQ Signals ORSPI4 Note: Refer to Technical Note TN1046 for more detailed board design guidelines for the ORSPI4 QDR Memory Controller. VDDMEM_IO VDDH (1.5V) 75 ohm ohm VDDMEM_IO 2 VDDH VTERM = 2 75 ohm ohm ...
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... Lattice Semiconductor Supported Data Rates The Memory Controller on the ORSPI4 device can support the following data rates. Table 74. Supported Data Rates (36-Bit QDR-II, 32 bit Considered Data) -1 Clock Frequency (DDR) Data Rate 156 MHz 19.97 Gbps 1. Data Rate = (Max. write data rate + Max. read data rate) for 32 bits of data. ...
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... PMIQ data in hold with respect to PMIC clock rising edge rh t PMIQ data in setup with respect to PMICN clock rising edge fs t PMIQ data in hold with respect to PMICN clock rising edge fh PMIC PMICN PMIQ Description 192 ORCA ORSPI4 Data Sheet Min Value Units -0.5 ns 2.0 ns -0.5 ns 2.0 ns ...
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... Power Supplies for ORSPI4 Power Supply Descriptions Table 77 shows the ORSPI4 FPGA and embedded core power supply groupings. VDD33 Is a 3.3V positive power supply used for 3.3 V configuration RAMs. VDD33_FPGAPLL is a 3.3V positive power supply for internal PLLs. When using PLLs, this power supply should be well isolated from all other power supplies on the board for proper operation. The fi ...
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... H - HSTL output buffer power supply of the QDR Memory Controller. DD – Supply REFI_1, REFI_2, REFI_3, REFI_4 - Voltage reference for HSTL input buffer of the QDR Memory Controller should be one-half VDDH and V pins are critical to system performance. An example DD SS A_SPIC, V A_SPID - Analog core 1.5V SPI supplies 194 ORCA ORSPI4 Data Sheet ...
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... ORCA ORSPI4 Data Sheet PIN 0.1 μf —1 NETWORK FOR EVERY 2 PINS V _ANA DD 0.1 μf —1 NETWORK FOR EVERY 2 PINS —1 EACH FOR V GB_[A, 0.1 μf — ...
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... ORCA ORSPI4 Data Sheet PIN V A_SPI DD 0.1 μf —1 NETWORK FOR EVERY 2 PINS V A_PLL DD 0.1 μf —1 NETWORK FOR EVERY 2 PINS VDD33_FPGAPLL 0.1 μf —1 NETWORK FOR EVERY 2 PINS REFI[1:4] 0.1 μf — ...
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... I/O These pins are user-programmable I/O pins if not used by PLLs after configuration. P[TBLR]CLK[1:0][TC] I Pins dedicated for the primary clock. Input pins on the middle of each side with differential pair- ing. I/O After configuration these pins are user programmable I/O, if not used for clock inputs. ORCA ORSPI4 Data Sheet Description After configuration 1 197 1 ...
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... I/O If not used for MPI these pins are user-programmable I/O pins after configuration. Description MPI data transfer strobe status indication, a high indicates mode this is driven low indicating the MPI received the data on the write cycle or 198 ORCA ORSPI4 Data Sheet ...
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... The timing of DONE release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user I/Os) is controlled by a second set of options. Description s width from 8, 16, 32-bit in MPI mode. Driven by the bus master in a write 199 ORCA ORSPI4 Data Sheet MPI interface. It can ...
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... Lattice Semiconductor ORSPI4 SPI4 External I/O Description This section describes device I/O signals to/from the SPI4 interface. Table 80 and Table 81 lists the external signals that interface to the SPI4 block. Table 80. SPI4 External Transmit Path Interface Signals Pin Name O = FPSC Output ( FPSC Input ...