ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 83

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Port Status Sequencer (PSS) Logic
In addition to formatting received data and sending it to the FPGA logic, the receive block also sends status infor-
mation to the SPI4 status interface. The Port Status Sequencer (PSS) block is responsible for providing port status
to the SPI4 Receive Status Protocol block (RSP) according to a pre-configured calendar sequence. Status is
derived from the fill-levels of the DPRAM FIFOs and/or from the FPGA status interface.
When status is provided by FPGA logic, the FPGA application writes status information to a 256 word PSS memory
in a random fashion. The PSS memory is addressed by an 8-bit port ID (SPIA_RX[32, 64 or 128]_PORT_ID[7:0]).
The data written to the memory is the SPIA_RX[32, 64 or 128]_STAT and an external status enable (SPIA_RX[32,
64 or 128]_EXT_STAT_EN) for the selected port. A write is initiated by the FPGA by asserting SPIA_RX[32, 64 or
128]_PSS_WE high and providing a clock on SPIA_RX[32, 64 or 128]_PSS_CLK.
The PSS block contains a main and shadow calendar table. Only one of these calendars is in use at a given time.
Once a calendar is provisioned with a certain sequence, it is not desirable to change the sequence in that calendar
during active device operation. To enable hitless switching of calendars, a shadow calendar is provided. The
RX_CAL_SEL control bit (Address 30916 for SPIA and 30A16 for SPIB) in the memory map controls the choice.
The choice to select a shadow calendar enables hitless bandwidth reprovisioning on the SPI4 link. While one cal-
endar is being used (e.g. main), the other calendar (shadow) can be configured independently with the desired
sequence. For more details, refer to the section on calendar programming.
The Port Status Sequencer (PSS) block polls for port status. It uses the calendar address to decide which port
should be polled for status. The status received from the polled port is then formatted into one of the SPI4 specified
status encodings (STARVING, HUNGRY, SATISFIED). For every port, the status is polled either from the internal
DPRAM FIFO flags or the user-provided status bits depending on the external status enable bit. When the external
status enable bit for a given port is set to ‘1’, it indicates that the status encoding for that port on the SPI4 bus is
decided by the external user. When set to ‘0’, the SPI4 status encoding is dictated by the status flags from the inter-
nal DPRAM banks.
The status bits sent to RSP from the PSS block is determined according to the truth table shown in Table 22. The
first four columns are the bits of information looked up for the current port ID, and the last column is the status that
is sent for that selected port to the RSP.
Table 22. Port Status Encoding
k = RX32 or RX64 or RX128
SPI4 Status Logic Blocks (RSP, RSO)
The SPI4 Receive Status Protocol (RSP) is responsible for FIFO status encoding, calendar management, status
pattern encoding (sync bits “11”), DIP-2 calculation and optional calendar selection word encoding (as proposed in
Appendix G of SPI4-02.0 specification).
The RSP block performs the following functions:
• Status frame creation
Virtual FIFO
fill 3 4 ⁄
≥
1
0
0
0
0
0
0
Virtual FIFO
fill 1 2 ⁄
≥
x
x
x
x
0
1
x
SPI[A,B]_k_EX
T_STAT_EN
1
1
1
0
0
1
x
83
SPI[A,B]_k_ST
AT[1:0]
“00”
“01”
“10”
“11”
x
x
x
ORCA ORSPI4 Data Sheet
Disabled link
SPI4 Status
SATISFIED
SATISFIED
STARVING
STARVING
Encoding
HUNGRY
HUNGRY