ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 84

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
• Decrements CALENDAR_M and CALENDAR_LEN counters
• DIP-2 calculation
The core of the RSP block is the state machine shown in Figure 32. The state machine is in the DISABLE state
upon reset. Setting the register bit RX_STATUS_DIS to ‘1’ or misalignment on the SPI4 RX data interface will
cause the state machine to reset to DISABLE state and start sending “11” on the SPI4 status bus. When the
received data is aligned and none of the other conditions apply, the state machine transfers to the SYNC state. The
SYNC state exists for only one clock cycle. In this state the calendar management counters are initialized with the
configured values from CALENDAR_LEN_RX and CALENDAR_M_RX. The next state is the CAL state if
CALENDAR_SW_EN bit is set to ‘0’ or the SWITCH state if CALENDAR_SW_EN bit is set to ‘1’. In the CAL state,
the counter for CALENDAR_LEN_RX is decremented on each cycle and the counter for CALENDAR_M_RX is
decremented at the end of each calendar sequence. If the CALENDAR_M_RX counter has not reached zero, the
CALENDAR_LEN_RX counter is reset. On each clock cycle, the status is sent out on the RLSTAT bus. The DIP-2
code is calculated in each clock cycle using the method (diagonal XOR) described in the OIF-SPI4-02.0 standard.
Once both calendar management counters have expired, the calendar management is complete and moves to the
DIP-2 state. The current DIP-2 value coming out of the CAL state is XOR’ed with “11”, the final 2-bit DIP-2 word is
sent out on the RLSTAT bus and the SYNC state is entered. If the RX_CAL_SW_EN bit is enabled (set to ‘1’) then
the RSP will insert an extra word into the FIFO status frame
Figure 32. RSP State Machine
The SPI4 Receive Status Output (RSO) block contains the low speed LVTTL buffers and LVDS output buffers nec-
essary for the output stage of receive status logic. The option to choose between LVTTL or LVDS outputs is
selected by the software register bit SPI4_STATUS_IO_SEL.
Calendar Programming
On a SPI4 link, FIFO status information is sent periodically over the status link (RSTAT bus on the SPI4 interface)
from the device that receives data. The calendar is a means by which the SPI4 link conveys information to a data
source about the availability of buffer space in the FIFOs that receive data from that data source. A calendar is a
sequence of status messages that
• Provides information on the buffer space for a port or traffic flow
• Allows user to allocate bandwidth for a port or flow depending on the overall traffic characteristics.
RESET
RESET
DISABLE
DIP-2
DESKEWED
CAL_DONE
RESET
RESET
84
SYNC
CAL
RX_CALENDAR_SW_EN= “0”
RX_CALENDAR_SW_EN = ‘1’
ORCA ORSPI4 Data Sheet
RX_CAL_LEN_MAIN/SHD,
RX_CAL_M_MAIN/SHD
SWITCH