ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 57

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
• If training is to be used, the user must also configure the 16-bit TX_ALPHA variable to indicate the number of
If the number of Bytes within the training sequences do not fill entire SPI4 Burst Cycle, the unused Byte fields will
be padded with Idle data in order to keep the training sequences aligned on 16 Byte boundaries.
Calendar Programming
On a SPI4 link, FIFO status information is received periodically over the status link (TSTAT bus on the SPI4 inter-
face) from the device that sources data. Calendar is a means by which the SPI4 link conveys information to the TX
data source about the availability of buffer space in the RX FIFOs that receive data from that data source. A calen-
dar is a sequence of status messages that:
• Provides information on the buffer space for a port or traffic flow.
• Allows user to allocate bandwidth for a port or flow depending on the overall traffic characteristics.
The SPI4 status channel operates at 1/8th the SPI4 data rate, which is reasonable because data is always sent in
16-byte bursts. Thus, the fastest status update can be expected once in every 8 data clock cycles. For a given port,
the frequency with which its status is reported to the far-end transmitter source depends on the allocated band-
width for the port. It is imperative that the transmitter and receiver devices are programmed with identical calendar
sequences. The following examples illustrate this:
Suppose a channelized STS-48 has three STS-12 ports and four STS-3 ports (channels), each STS-12 port
should have four times the bandwidth of an STS-3 port and 12 times the bandwidth of an STS-1 port within a single
calendar cycle. The first step is to map each port to an 8-bit Port ID (address) as shown in Table 23
Table 10. Port ID Mapping
The calendar sequence is as follows:
A1, A2, A3, B1, A1, A2, A3, B2, A1, A2, A3, B3, A1, A2, A3, B4
The number of calendar entries is thus 16. This calendar sequence is programmed in the transmit calendar mem-
ory as follows:
• This example uses the main calendar. The calendar memory is selected by setting the TX_CAL_MEM_SEL bit
• Writes are done to addresses 0x31000 - 0x3100F. This will correspond to entries 0x00 - 0x0F in the calendar
• After programming the calendar memory, the TX_CAL_MEM_SEL bit is set to ‘0’.
• The calendar length register TX_CAL_LEN_MAIN is set to 16 (address 30922 and 30923 in SPIA, 30A22 and
times the training pattern is to be repeated. By default the value is 0x0000 which disables the training pattern.
(address 30917 in SPIA and address 30A17 in SPIB) to ‘1’.
memory. This is shown in Table 11. Note that the main calendar memory has 1023 locations and can be pro-
grammed through addresses 0x31000 - 0x313FE. The shadow calendar memory also has 1023 locations and
can be programmed through addresses 0x31400 - 0x317FE.
30A23 in SPIB).
Port
A1
A2
A3
B1
B2
B3
B4
Bandwidth
STS-12
STS-12
STS-12
STS-3
STS-3
STS-3
STS-3
57
(Port Address)
8-Bit Port ID
0x00
0x01
0x02
0x03
0x04
0x05
0x06
ORCA ORSPI4 Data Sheet