ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 7

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
• For low speed data, static alignment can be selected through a programmable control bit
• Single-link and multi-link operation.
• SPI4 transmit data protocol support logic
• Handles all credit calculations based on the status information automatically
• Provides optional signals to FPGA interface logic for flow control:
• Embedded Calendar-based port polling sequence mechanism and bandwidth allocation for all 256 ports
• Two calendars are supported in each direction
• Transmit and Receive Status FIFOs provided to store flow control information for up to 256 ports.
• Support for various options for flow control status creation, selectable per port:
• Dual-port RAM interface to the FPGA supports flexible data widths for both the receive and transmit FPGA/core
• Training pattern generation
interfaces.
– Speeds up to 350 MHz DDR (700 Mbits/s throughput)
– Dynamic alignment is bypassed and disabled to save power in static alignment mode.
– Programmable on-edge or on-center clock/data relationship option at receiver.
– Programmable clock delay
– Combines the data and control words from the transmit FIFO (DPRAMs) into the SPI4 format
– Performs DIP-4 calculation over data and control words on the TX side and inserts into the payload control
– Current transmit Port ID (Calendar Port or user specified port # per calendar port)
– Current BURST_VAL Parameter for that Port
– Status from that Port
– Programmable transmit and receive calendar tables support up to 256 ports
– Main Calendar (1K deep)
– Shadow Calendar (also 1K deep). User can reconfigure second calendar while operating off main calendar,
– All calendar configuration parameters specified in the standard (CALENDAR_LEN, CALENDAR_M, etc.) are
– Performs Status frame creation
– DIP-2 odd parity calculated over the status frames
– Supports either quarter-rate LVDS or LVTTL status channels
– Based on DPRAM FIFO fill levels
– Based on status from FPGA interface per port
– Both of the above
– Scalable data bus enables users to configure TX interface for their respective port bandwidth requirements
– A total of 4 DPRAM banks where each of the DPRAMs can be logically partitioned into 1, 2, 4, or 8 virtual
– Used for temporary storage and clock domain crossing
– Can be configured to provide 32-, 64-, 128-bit data bus interfaces from the FPGA (plus accompanying con-
– 32-bit mode: Four banks are separate and accessed independently
– 64-bit mode: Banks 0 & 1 become a single aggregation and Banks 2 & 3 become a single aggregation
– 128-bit mode: All four banks become a single aggregation
– Mixed mode: One 64-bit (two banks become a single aggregation) and two banks are separate and
– User controlled “alpha” repetitions of training pattern in TX_DATA_MAX_T intervals
– Automatic generation of training pattern during loss of synchronization
word
and then switch on the next cycle to allow hitless operation
supported
FIFOs
trol signals)
accessed independently
7
ORCA ORSPI4 Data Sheet