ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 37

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 3. SPIA Core Transmit FPGA Interface in 64-Bit Mode (Continued)
Table 4. SPIA Core Transmit FPGA Interface in 128-Bit Mode
Note: For SPIB replace A with B
Note: For SPIB replace A with B
DPRAM
DPRAM
Status
Misc.
I/Os
/Os
Lattice Semiconductor
1
0
SPIA_TX64_ERR_1
SPIA_TX64_WE_1
SPIA_TX64_PORT_1[7:0]
SPIA_TX64_WD_CNT_RST_
1
SPIA_TX64_LINK_DIS_1
SPIA_TX64_CLK_1
SPIA_TX64_FIFO_FULL_1
SPIA_TX64_PORT_ID[7:0]
SPIA_TX64_STAT[1:0]
SPIA_TX64_BURST_VAL[3:0]
SPIA_TREFCLK_X8
SPI_SATM_A
SPIA_TX128_ADDR[2:0]
SPIA_TX128_DATA[127:0]
FPGA Interface I/Os
FPGA Interface I/Os
FPGA → Core ‘0’ - Incoming ATSCLK is assumed to be edge-aligned with the data and
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core
FPGA → Core User Write data. A single write will complete an entire 128-bit line.
Core →FPGA
Core →FPGA
Core →FPGA
Core →FPGA
Direction
Direction
From/To
From/To
Packet error indication. A '1' indicates an error has occurred for the current
packet being transmitted. The ERR signal must be asserted coincident with
the EOP signal.
When an EOP is detected by the DPRAM Write Pointer Logic, the address
pointer will be automatically incremented to the next location within the
FIFO partition range.
Write Enable. A logic '1' causes data on the SPIA_TX64_DATA_1[63:0] bus
to be captured for a write to the DPRAM.
SPI4 port indicator, used to associate the current transmit data with a par-
ticular port number.
Line Write Termination indicator. This signal causes the FIFO write address
pointer within the embedded core to increment to the next address location
for the addressed partition. This signal can be used for custom applications
as well as for diagnostic test functions.
Link disable control signal. When asserted to a logic '1', the AMA will cease
polling from a DPRAM. All ports associated with a disabled DPRAM will
remain unserviced until the control signal is deasserted. The AMA will send
IDLE data across the SPI4 link. If the application continues to write data to
that port FIFO, it will eventually fill and provide proper FIFO fill status to the
application.
Transmit write clock reference. The clocks across the different transmit
interfaces are independent from each other, and are not required to be syn-
chronous to each other.
FIFO full status. The status is given in response to the assertion of any
valid address on the SPIA_TX64_ADDR_1[2:0] bus. This signal will be
asserted to a logic '1' when the current FIFO partition has crossed the con-
figured fill level within the partition.
Port number of the currently serviced SPI4 data port. The value can either
be the actual SPI4 value or a programmed user value. Further details are
provided in the TX Calendar Control Logic description.
Status of the SPI4 port currently being serviced. These signals can be
used in conjunction with the FIFO partition FIFO to police transmit traffic
congestion for a particular SPI4 port.
Indicates the number of SPI4 cycles the currently active port will be ser-
viced. Each cycle indicates an attempt to read 128 bits of data from the
respective FIFO partition.
Transmit reference clock. This clock signal is 1/4th the SPI4 clock. This sig-
nal can be used to synchronize FPGA application logic to the FPSC logic.
centered to the data eye within the chip.
‘1’ - Incoming ATSCLK is assumed to be skewed with respect to the data
off-chip.
Virtual FIFO Write Address. Each DPRAM can be divided up to a maximum
of eight partitions. When operating in 128-bit mode, each partition will be 4x
the depth of the corresponding partition in 32-bit mode. More than one port
can be configured to share a virtual FIFO partition.
37
Description
Description
ORCA ORSPI4 Data Sheet