ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 157

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 47. Memory Map (Continued)
Lattice Semiconductor
SERDES Alarm Mask Registers (Read/Write), x = [A, ...,D]
30001
30011
30021
30031
SERDES Common Transmit and Receive Channel Configuration Registers (Read/Write), x = [A, ...,D]
30002
30012
30022
30032
30003
30013
30023
30033
Address
Abso-
(0x)
lute
[0]
[1]
[2:7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5:7]
Bit
Reserved
MLKI_x
Reserved
TXHR_x
PWRDNT_x
PE0_x
PE1_x
HAMP_x
Reserved
Reserved
8b10bT_x
RXHR_x
PWRDNR_x
Reserved
8b10bR_x
LINKSM_x
Reserved
Name
FF
00
20
Reset
Value
(0x)
Reserved. Must be set to “1”.
Set to “1” on device reset.
Mask Receive PLL Lock Indication, Channel x.
Transmit Half Rate Selection Bit, Channel x.
When TXHR_x = “1”, HDOUT_x's baud rate = (REFCLK*10) and TCK78
=(REFCLK/4); when TXHR_x=0, HDOUT_x's baud rate = (REFCLK*20) and
TCK78=(REFCLK[A:B]/2).
TXHR_x = 0 on device reset.
Transmit Powerdown Control Bit, Channel x. When PWRDNT_x = “1”, sec-
tions of the transmit hardware are powered down to conserve power.
PWRDNT_x = 0 on device reset.
Transmit Preemphasis Selection Bit 0, Channel x. PE0_x and PE1_x select
one of three preemphasis settings for the transmit section.
Transmit Half Amplitude Selection Bit, Channel x. When HAMP_x = “1”, the
transmit output buffer voltage swing is limited to half its normal amplitude.
Otherwise, the transmit output buffer maintains its full voltage swing.
HAMP_x = 0 on device reset.
Reserved. Must be set to 0
Set to “0” on device reset.
Transmit 8b/10b Encoder Enable Bit, Channel x. When 8b10bT_x = “1”, the
8b/10b encoder in the transmit path is enabled. Otherwise, the data is
passed unencoded.
8b10bT_x = “0” on device reset.
Receive Half Rate Selection Bit, Channel x.
When RXHR_x =”1”, HDIN_x's baud rate = (REFCLK*10) and
RCK78=(REFCLK/4); when RXHR_x= “0”, HDIN_x's baud rate = (REF-
CLK*20) and RCK78=(REFCLK/2).
RXHR_x = “0” on device reset.
Receiver Power Down Control Bit, Channel x. When PWRDNR_x = 1, sec-
tions of the receive hardware are powered down to conserve power.
PWRDNR_x = “0” on device reset.
Reserved. Must be set to “1”.
Set to “1” on device reset.
Receive 8b/10b Decoder Enable Bit, Channel x. When 8b10bR = “1”, the
8b/10b decoder in the receive path is enabled. Otherwise, the data is
passed undeocded.
8b10bR_x = “0” on device reset.
Link State Machine Enable Bit, Channel x. When LINKSM_x = “1”, the
receiver Fiber Channel link state machine is enabled. Otherwise, the Fibre
Channel link state machine is disabled.
NOTE: LINKSM_x is ignored when XAUI_MODE_x= “1”.
LINKSM_x = “0” on device reset.
PEO_x=PE1_x = 0, Preemphasis is 0%
PEO_x=1, PE1_x = 0 or PEO_x=0, PE1_x = 1, Preemphasis is 12.5%
PEO_x=PE1_x = 1, Preemphasis is 25%.
PEO_x=PE1_x = 0 on device reset.
157
Description
ORCA ORSPI4 Data Sheet