ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 44

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Figure 15. 128-Bit Write Protocol
SPI4 Transmit Interface - Detailed Description
The FPGA transmit interface provides a simple FIFO-like interface, simplifying write accesses. Asserting the cor-
rect 3-bit address with the associated write enable signal causes transmit data and sideband control signals to be
registered for writes to a FIFO partition within the DPRAMs. When addressing a particular FIFO partition within the
DPRAM, the associated FIFO fill level of the addressed partition is immediately reflected back to the FPGA,
enabling the user to monitor the current fill level of a particular partition. Based upon the configured fill level, a logic
'1' on the FIFO_FULL signal will indicate either a 3/4-full condition or a completely full condition for the indexed par-
tition.
Transmit DPRAMs
There are four DPRAMs referred to as banks 0, 1, 2 and 3. Each bank has a 32-bit data interface to the FPGA.
Each DPRAM has its own individual write enable and write clock allowing it to be written by the FPGA application
independently.
Each DPRAM bank is configured by software to operate in either 32-bit, 64-bit or 128-bit aggregation mode. Every
DPRAM bank is also configured to contain 1, 2, 4 or 8 virtual FIFOs. The user determines the number of FIFOs
depending on the number of ports and buffer requirements for the ports as required by a given application. The pro-
gramming of a DPRAM bank in 32-bit, 64-bit or 128-bit mode and programming of the number of virtual FIFOs
within a DPRAM bank is done through software as shown in Table 8. Note that in 64-bit mode, DPRAMs 0 and 1
must be configured identically. The combined DPRAM pair is referred to as DPRAM “0”. Similarly DPRAM pairs 2
and 3 must be configured identically. This combined DPRAM pair is referred to as DPRAM “2”. In 128-bit mode, all
DPRAMs must be configured identically. The combined DPRAM banks are collectively referred to as DPRAM “0”.
The aggregation modes can be used in five possible combinations as shown in Table 6. The size of the embedded
data and control FIFOs for each mode is shown in Table 7. The user accesses a virtual FIFO using the 3-bit FIFO
read address (refer to Table 2, Table 3, and Table 4) from the FPGA. Table 5 shows the indexed partition based
upon the configured DPRAM partitioning and aggregation mode.
SPIA_TX128_CLK
SPIA_TX128_ADDR[2:0]
SPIA_TX128_WE
SPIA_TX128_DATA[127:0]
SPIA_TX128_BE[7:0]
SPIA_TX128_SOP
SPIA_TX128_EOP
SPIA_TX128_PORT[15:0]
SPIA_TX128_WD_CNT_RST
NOTE: SPIB is identical to SPIA
0xFFFF
Part. Addr 'k'
1
Port 3
44
0xFFF8
2
0xFFFF
Addr 'j'
Port 7
3
0xFFFF
4
Partition Addr 'j+4'
ORCA ORSPI4 Data Sheet
Port 2
0xFFFF
5
6