ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 182

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
The dynamic alignment timing budget for a data transfer between two ORSPI4 devices is shown in Table 62.
Table 62. Data Path Parameters for Dynamic Alignment.
With PRBS 2^7-1 data pattern, all channels operating, FPGA logic active, 900 Mbit/s data rate with 112.5 Mhz REFCLK, REFCLK jitter of 30 ps,
SPI4.2 Status Interface
System Timing Reference Points
Figure 93 shows the system timing reference points A and B for status channel timing parameters listed in Table
63.
Figure 93. Status Channel Reference Points
Figure 94. Status Channel Reference Points with Respect to Clock Edge (LVDS and LVTTL I/Os)
T
J
= -40º C to 125º C, 1.425 V to 1.575 V supply. Jitter measured with a Wavecrest SIA-3000.
Note: Only status signals are shown
TSTAT
TSCLK
RSTAT
RSCLK
Description
Transmit clock jitter
Transmit data jitter with respect to clock edge
Receive clock jitter tolerance
(C)
T
dia
Source
Launch Edge
T
dib
t
s
(D)
D
Capture Edge
TSTAT[1:0] /
RSTAT[1:0]
TSCLK/RSCLK
t
h
182
C
(UI peak-to-peak)
Value
0.11
0.09
0.60
Sink
ORCA ORSPI4 Data Sheet