ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 51

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Transmit Data Output (TDO) Logic Block
The Transmit Data Output (TDO) block contains the high-speed serializer, which uses an x8 clock, synthesized by
an internal PLL, to generate the high-speed data from the low-speed 128-bit data. Data is transmitted off-chip
using a 16-bit LVDS data bus TDAT[15:0], a LVDS control bit TCTL and a source synchronous clock TDCLK. The
16-bit data bus and control are DDR signals relative to the TDCLK. The LVDS buffers contained within the TDO are
fully compliant with SPI4 electrical specifications.
The TDO uses the internal embedded core transmit reference clock (TREFCLK) to generate an x4 TDCLK. The
TDCLK and TREFCLK are both derived from the user-provided reference clock. The TREFCLK is used as the sys-
tem clock for the entire Transmit SPI4 interface logic. The TREFCLK is also sent to the FPGA for the customer to
use as a synchronizing signal source if desired.
In order to support 10 Gbits/s throughput, the minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz
DDR). For applications that require less than 100 - 200 Mbits/s on TDCLK, the PLL in the TDO block can be
bypassed. This allows for operation as low as 100 MHz on the Transmit SPI4 link.
Figure 18. Transmit Calendar and Status Block
Transmit Calendar (TCC) Logic Block
The Transmit Calendar Block (TCC) is responsible for maintaining the transmit main and shadow calendars, provid-
ing port service information to the AMA, integrating transmit status update information into the servicing of ports
according to the SPI4 specification, and providing port service information to the FPGA for traffic monitoring.
To
FPGA
I/F
Note: SPIA is identical to SPIB
k = 32, 64, or 128
SPI[A,B]_TX_k_PORT_ID
SPI[A,B]_TX_k_STAT
SPI[A,B]_TX_k_BURST_VAL
AMA_ID
8
2
4
TX CALENDAR
To AMA
Control
Logic
51
BURST_VAL
PORT_ID
PORT_STAT
TSP
TLSCLK
ORCA ORSPI4 Data Sheet
TLSTAT
TSI
ATSCLK
ATSTAT
From
External
I/O