ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 29

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Far-end status is received by the TSI block and sent to the TSP block for buffering. The interface supports quarter-
rate status from either LVDS or TTL inputs. The TSP block provides both the port identification and current status to
the TX Calendar Control Logic, where internal tables are updated accordingly to provide proper port servicing.
ORSPI4 Transmit FPGA/Embedded Core Interface Description
The FPGA I/O interface to the ORSPI4 logic supports several interface features and varying interface characteris-
tics, depending upon the configured mode of operation. The modes are referred to as 'aggregation modes' due to
the nature of the aggregation of data busses for the different modes of operation. There are three data aggregation
modes supported by the Transmit Core:
• 32-bit mode: Each of the 4 DPRAMs can be configured to use a 32-bit user data interface plus associated control
• 64-bit mode: DPRAM pairs {[0:1], [2:3]} are configured to serve as 64-bit user data interfaces, plus associated
• 128-bit mode: All four DPRAM banks are aggregated into a single FIFO with a 128-bit user-data interface from
• To maintain compliance with the SPI-4.2 interface protocol, the user is required to burst a minimum of 16 data
Several other features are:
• Auto-increment of the DPRAM write address pointer when an EOP is detected.
• Prohibit data writes if no associated byte-enable (BE) bits are asserted within an entire 128-bit line, optimizing
• The ability for the user to disable one or more of the interface links using the SPI[A,B]_k_LINK_DIS_j signals.
• The ability for the user to reset a port’s write pointer with the SPI[A,B]_k_WD_CNT_RST_j signal. This can be
• The ability for the user to individually poll for DPRAM FIFO fill status. Normal FIFO status is provided whenever
Table 2 lists the I/Os for the Transmit SPI4A core only. The interface signals for core B are identical with the names
modified appropriately.
Table 3 and Table 4 list the I/O for the Transmit SPI4 core for 64-bit and 128-bit aggregation modes respectively.
signals across the FPGA interface. This interface is useful when interfacing the SPI4 data pipe to one or more
sub-rate channels. This mode provides up to 4 independent 32-bit interfaces. In this mode, the interfaces do not
need to be synchronous with each other.
control signals. Note that 32-bit and 64-bit modes can be combined to provide up to 3 independent interfaces.
the FPGA.
bytes per write period. This is required for all modes of aggregation. For 32-bit mode, four writes are required, for
64-bit mode, two writes are required. For 128-bit mode, a single write access will provide 16 bytes of data.
the FIFO memory locations by not wasting memory.
This causes the AMA logic to cease polling from a DPRAM. All ports associated with a disabled DPRAM will
remain unserviced until the control signal is deasserted.
used to customize data applications or as a diagnostic test function.
the user attempts to write data to the DPRAMs. If an address is provided to the FIFO without a write enable,
FIFO status is still provided. This feature is useful when the application requires knowing the status of individual
virtual FIFOs but is not prepared to write data to it.
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ORCA ORSPI4 Data Sheet