ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 120

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
The receiver section receives high-speed serial data at its differential CML input port and sends it in to the Clock
and Data Recovery (CDR) block. The CDR block then generates a recovered clock (RWCKx) and retimes the data.
Thus, the recovered receive clocks are asynchronous between channels.
Transmit Clock Source Selection
The TCKSEL[A:B] bit select the source channel of TCK78. The selection of the source for TCK78 is controlled by
this bit as shown in Table 32.
Table 32. TCK78 Source Selection
Recommended Transmit Clock Distribution for the ORSPI4
As an example of the recommended clock distribution approach, TSYS_CLK_[A:D] can be sourced by TCK78 as
shown in Figure 58 if the transmit line rate are common for all four channels in a quad.
Figure 58. Transmit Clocking for a Single Block
If the transmit line rate is mixed between half and full rate among the channels, then the scheme shown in Figure
59 can be used. The figure shows TSYS_CLK_A and TSYS_CLK_B being sourced by TCK78 and TSYS_CLK_C
and TSYS_CLK_D being sourced by TCK78/2 (the division is done in FPGA logic). Similar clocking would be used
for Quad B.
All Clocks at
78.125 MHz
FPGA
Logic
TSYS_CLK_B
TSYS_CLK_A
TSYS_CLK_D
TSYS_CLK_C
TCK78
TCKSEL0
0
1
0
1
Common Logic
Channel C
Channel D
Channel A
Channel B
TCKSEL1
0
0
1
1
120
Clock Source
Channel C
Channel C
Channel A
Channel B
2
Outgoing Serial Data
Four Channels of
REFCLK[P:N]
156.25 MHz
3.125 Gbits/s
ORCA ORSPI4 Data Sheet