ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 105

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Backplane Transceiver Core Detailed Description
The following sections describe the various logic blocks in the SERDES portion of the FPSC. For a detailed
description of the programmable logic functions, please see the ORCA Series 4 FPGA Data Sheet and related
application and technical notes.
The major functional blocks in the SERDES include:
• One SERializer-DESerializer (SERDES) block and Clock and Data Recovery (CDR) circuitry
• 8b/10b encoder/decoders
• Transmit pre-emphasis circuitry
• 4-to-1 multiplexers (MUX) and 1-to-4 demultiplexers (DEMUX)
• Fibre channel synchronization state machine
• XAUI link alignment state machine
• Alignment FIFOs
A top level block diagram of the SERDES Logic is shown in Figure 48.
Figure 48. Top Level Block Diagram, SERDES Embedded Core Logic
RCK78
RSYS_CLK_1
RSYS_CLK_2
CV_SELx
SYS_RST_N
FPGA_RESET_FC
FPGA
Logic
TCOMMA[3:0]
TSYS_CLK_A
TWDA[31:0]
MRWDA[39:0]
CV_SELA
RWCKA
.
.
.
RCK78
TCK78
Core →FPGA
FPGA → Core Low-speed receive FIFO clock for channels A, B
FPGA → Core Low-speed receive FIFO clock for channels C, D
FPGA → Core Enable detection of code violations in the incoming data
FPGA → Core Synchronous reset of the channel alignment blocks.
FPGA → Core Disables access to SERDES when high
Alignment
2:1 MUX
Channel
Multi -
Block
(x40)
Interface and
MUX Block
Receive low-speed clock to FPGA—SERDES Quad.
Channel B
Channel C
Channel D
Logic Common to Quad
DEMUX
Block
105
Link State
Machine
Transmit Channel A
Receive Channel A
TX SERDES
DES Block
Block
RX SER-
ORCA ORSPI4 Data Sheet
2
2
2
REFCLK[P:N]
HDIN[P:N]_A
HDOUT[P:N]_A
.
.
.
Backplane
Serial
Links