ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 153

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
ORCA ORSPI4 Data Sheet
Software Reset (SOFT_RESET_S4A)
A register bit used to reset the SPIA is SOFT_RESET_ S4A (30B20, bit 6). This bit, when set to “1”, disables the
SPIA block.
FPGA Interface Reset (FPGA_RESET_S4A)
FPGA_RESET_S4A performs the same function as SOFT_RESET_ S4A. The difference is that it is an FPGA
interface signal instead of a configuration register bit.
SPIB-only Resets
The SPIB block can be individually reset though Software Reset-via the microprocessor interface, or using an
FPGA interface signal.
Software Reset (SOFT_RESET_S4B)
A register bit used to reset the SPIB is SOFT_RESET_ S4B (30B20, bit 7). This bit, when set to “1”, disables the
SPIB block.
FPGA Interface Reset (FPGA_RESET_S4B)
FPGA_RESET_S4B performs the same function as SOFT_RESET_ S4B. The difference is that it is an FPGA
interface signal instead of a configuration register bit.
MC-only Resets
The Memory Controller (MC) block can be individually reset though Software Reset-via the microprocessor inter-
face, or using an FPGA interface signal.
Software Reset (SOFT_RESET_MC)
A register bit used to reset the MC is SOFT_RESET_ MC (30B20, bit 5). This bit, when set to “1”, disables the MC
block.
FPGA Interface Reset (FPGA_RESET_MC)
FPGA_RESET_MC performs the same function as SOFT_RESET_ MC. The difference is that it is an FPGA inter-
face signal instead of a configuration register bit.
SERDES-only Resets
The SERDES block can be individually reset though Software Reset-via the microprocessor interface, or using
FPGA interface signals.
Software Reset (SWRST and HARD_RESET_FC)
Using the software reset option via the microprocessor interface, each channel can be individually reset by setting
SWRSTx (bit 2) to a logic “1” in the channel configuration register (30004,30014,30024,30034)). The device will be
ready 3 ms after the SWRSTx bit is de-asserted. Similarly, all four channels per quad SERDES can be reset by set-
ting the global reset bit GSWRST (30005, bit 2). The device will be ready for normal operation 3 ms after the
GSWRST bit is de-asserted. Note that the software reset option resets only SERDES internal registers and
counters. The microprocessor registers are not affected. It should also be noted that the embedded block couldn't
be accessed until after FPGA configuration is complete. Also note that the SWRSTx and GSWRST are active
when the corresponding memory map register bit is set high.
Another register bit used to reset the SERDES is HARD_RESET_FC (30B20, bit 4). This bit, when active, disables
the SERDES and prevents any access to its internal microprocessor registers (300xx range).
FPGA Interface Reset signals (SYS_RST_N and FPGA_RESET_FC)
FPGA_RESET_FC performs the same function as HARD_RESET_FC. The difference is that it is an FPGA inter-
face signal instead of a configuration register bit.
SYS_RST_N is a synchronous active low reset FPGA interface signal. This signal, when active, resets the read
side of the multi-channel alignment FIFOs.
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