ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 167

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 47. Memory Map (Continued)
Lattice Semiconductor
30919A
30A19B
3091A A
30A1A B
3091B A
30A1B B
3091C A
30A1C B
3091D A
30A1D B
SPI4 Core TX Status Registers (Read and Write)
30928 A
30A28 B
30929 A
30A29 B
Address
Abso-
(0x)
lute
[0:7]
[0:7]
[0:7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0:1]
[2]
[3:4]
[5]
[6]
[7]
[0:7]
[0:7]
Bit
RX_DPRAM_1_FIFO
_URRUN_STS
RX_DPRAM_2_FIFO
_URRUN_STS
RX_DPRAM_3_FIFO
_URRUN_STS
RX_PLL_LOL_STS
RX_BAS_DONE_ST
S
RX_BAS_ERR_STS
RX_DSKW_DONE_S
TS
RX_DSKW_ERR_ST
S
RX_TRN_DET_STS
RX_ALGN_OFF_ST
S
TX_STATUS_LOF_S
TS
Reserved
RX_ILLEGAL_CTL_
STS
Reserved
RX_DIP4_ERR_STS 00
TX_DIP2_ERR_STS
RX_ASYNC_FIFO_O
VERRUN_STS
TX_DPRAM_0_FIFO
_OVERRUN_STS
TX_DPRAM_1_FIFO
_OVERRUN_STS
Name
00
00
00
00
0
00
00
Reset
Value
(0x)
Underrun status of bank 1 DPRAM FIFOs 0 to 7. These are enabled by
RX_DPRAM_FIFO_URRUN_INT_EN[1] (register 30912[A], 30A12[B]).
These bits clear when read, but will set immediately if the condition persists.
Underrun status of bank 2 DPRAM FIFOs 0 to 7. These are enabled by
RX_DPRAM_FIFO_URRUN_INT_EN[2] (register 30912[A], 30A12[B]).
These bits clear when read, but will set immediately if the condition persists.
Underrun status of bank 3 DPRAM FIFOs 0 to 7. These are enabled by
RX_DPRAM_FIFO_URRUN_INT_EN[3] (register 30912[A], 30A12[B]).
These bits clear when read, but will set immediately if the condition persists.
Status flag for loss of lock in PLL within the SPI4 receive core. This flag is
enabled by RX_PLL_LOL_INT_EN (register 30913[A], 30A13[B]).
Status flag for SPI4 receive core completing the baselining process. Base-
lining is the self-alignment power-up process that the macro does after it
detects lock of the PLL. This flag is enabled by RX_BAS_DONE_INT_EN.
(register 30913[A], 30A13[B])
Status flag for SPI4 receive core failing its internal self-alignment process.
This flag is enables by RX_BAS_INT_EN (register 30913[A], 30A13[B]).
Status flag for SPI4 receive dynamic alignment complete. This flag is
enabled by RX_DSKW_DONE_INT_EN.
Status flag for SPI4 receive core failing to dynamically align. This flag is
enabled by RX_DSKW_ERR_INT_EN (register 30913[A], 30A13[B]).
Status flag for SPI4 receive core detecting training patterns. This flag is
enabled by RX_TRN_DET_INT_EN (register 30913[A], 30A13[B]).
Status flag for loss of data alignment due to excess consecutive DIP4 errors.
This flag is enabled by RX_ALIGN_OFF_INT_EN (register 30913[A],
30A13[B]).
Status flag for TX status frame having too many consecutive DIP2 errors.
This flag is enabled by TX_STATUS_LOF_INT_EN (register 30913[A],
30A13[B]).
Status flag indicating that an illegal control work was received
Status flag for DIP4 error
Flag for error in framing TSTAT[0:1] inputs. This can be an unexpected 11
pattern or a DIP2 error.
Status flag for RX FIFO overrun inside S4RDP block.
Overrun status of bank 0 TX DPRAM FIFOs 0 to 7. These are enabled by
TX_DPRAM_FIFO_OVERRUN_INT_EN[0]. These bits clear when read, but
will set immediately if the condition persists. This will happen when writing to
the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high.
Overrun status of bank 1 TX DPRAM FIFOs 0 to 7. These are enabled by
TX_DPRAM_FIFO_OVERRUN_INT_EN[1]. These bits clear when read, but
will set immediately if the condition persists. This will happen when writing to
the DPRAM FIFOs while SPI[A,B]_k_FIFO_FULL_j is high.
167
Description
ORCA ORSPI4 Data Sheet