ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 147

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Software
Software for Configuration
There are two ways to write to the ORSPI4 memory map either via MPI (Microprocessor Interface) or via UMI (User
Master Interface) to the FPGA logic. Both the interfaces use the system bus to perform the transactions with the
registers. The MPI is provided to talk to any Power PC microprocessor whereas UMI is used for any customer-
defined interface and interfaces extremely well with ORCASTRA™ to graphically change and monitor the register
map. The registers are divided into different domains, the details of which can be found in the technical note
TN1017. ORSPI4 device core registers can be accessed by addressing the 30000 onwards domain. Since there
are four different macros inside the ORSPI4 core, all these macros have been assigned their individual sub
domains.
Table 43. Address Allocation - Register Elements
ORSPI4 Start-up Sequence
SPI4 Link Start-up Protocol
Immediately after reset, and before the link synchronization, the SPI4 link must initialize to a known interface proto-
col. This section describes the initialization protocol for a generic SPI4 link. The actual start-up procedure with the
appropriate software register settings is described in the next section. Figure 86 shows the SPI4 link reference dia-
gram that is referenced in the descriptions below. Where appropriate, the corresponding ORSPI4 software register
settings are also described as relevant to this start-up protocol.
A reset can be either hard or soft, but is assumed that the entire SPI4 link is being reset. Immediately after the
reset signal is deasserted and before the link synchronization, the following actions/conditions must occur/exist.
Figure 86. SPI4 Link Functional Block Diagram
1. The Receive Data FIFOs are emptied (RX_D_B)
DIP2 = “OK”
Device A
Address (0x)
30Axx
30Bxx
TX_D_A
309xx
308xx
TX_S_A
SPIA addresses
SPIB addresses
SERDES addresses
QDR MEM controller addresses and
some shared by SPIA and SPIB
147
Description
RX_D_B
RX_S_B
Device B
DIP4 = “OK”
ORCA ORSPI4 Data Sheet