ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 73

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 13. SPIA Core Receive FPGA Interface in 64-Bit Mode
Note: For SPIB replace A with B
DPRAM
Lattice Semiconductor
0
1
SPIA_RX64_ADDR_0[2:0]
SPIA_RX64_DATA_0[63:0]
SPIA_RX64_BE_0[7:0]
SPIA_RX64_CTL_0
SPIA_RX64_SOP_0
SPIA_RX64_EOP_0
SPIA_RX64_ERR_0
SPIA_RX64_FIFO_EMPTY_0 Core →FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]
ASTOP_ON_EOP0
SPIA_RX64_CLK_0
SPIA_RX64_RD_0
SPIA_RX64_ADDR_1[2:0]
SPIA_RX64_DATA_1[63:0]
SPIA_RX64_BE_1[7:0]
SPIA_RX64_CTL_1
SPIA_RX64_SOP_1
SPIA_RX64_EOP_1
SPIA_RX64_ERR_1
SPIA_RX64_FIFO_EMPTY_1 Core →FPGA FIFO Empty flag. Depends on the RX_DPRAM_EMPTY_TYPE_SELA[0]
ASTOP_ON_EOP1
SPIA_RX64_CLK_1
SPIA_RX64_RD_1
FPGA Interface I/Os
FPGA → Core FIFO read address.
Core →FPGA FIFO read data.
Core →FPGA Byte enables
Core →FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX64_DATA_0 bus contains
Core →FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.
Core →FPGA End of Packet Indicator. A ‘1’ indicates end of packet.
Core →FPGA Error. A ‘1’ indicates an error in the current word.
FPGA → Core Timing control for handling end of packet.
FPGA → Core FIFO read clock.
FPGA → Core FIFO read enable.
FPGA → Core FIFO read address.
Core →FPGA FIFO read data.
Core →FPGA Byte enables
Core →FPGA Port ID indicator. A ‘1’ indicates that the SPIA_RX64_DATA_1 bus contains
Core →FPGA Start of Packet Indicator. A ‘1’ indicates start of packet.
Core →FPGA End of Packet Indicator. A ‘1’ indicates end of packet.
Core →FPGA Error. A ‘1’ indicates an error in the current word.
FPGA → Core Timing control for handling end of packet.
FPGA → Core FIFO read clock.
FPGA → Core FIFO read enable.
Direction
From/To
Bit 7 - Byte enable for SPIA_RX64_DATA_0[63:56]
Bit 6 - Byte enable for SPIA_RX64_DATA_0[55:48]
Bit 5 - Byte enable for SPIA_RX64_DATA_0[47:40]
Bit 4 - Byte enable for SPIA_RX64_DATA_0[39:32]
Bit 3 - Byte enable for SPIA_RX64_DATA_0[31:24]
Bit 2 - Byte enable for SPIA_RX64_DATA_0[23:16]
Bit 1 - Byte enable for SPIA_RX64_DATA_0[15:8]
Bit 0 - Byte enable for SPIA_RX64_DATA_0[7:0]
the port ID.
software register bit in address 0x30920. When this bit is set to ‘0’, (default)
the empty flag indicates truly empty.
When this bit is set to ‘1’, the empty flag indicates that the FIFO is 1/4 full -1.
Bit 7 - Byte enable for SPIA_RX64_DATA_1[63:56]
Bit 6 - Byte enable for SPIA_RX64_DATA_1[55:48]
Bit 5 - Byte enable for SPIA_RX64_DATA_1[47:40]
Bit 4 - Byte enable for SPIA_RX64_DATA_1[39:32]
Bit 3 - Byte enable for SPIA_RX64_DATA_1[31:24]
Bit 2 - Byte enable for SPIA_RX64_DATA_1[23:16]
Bit 1 - Byte enable for SPIA_RX64_DATA_1[15:8]
Bit 0 - Byte enable for SPIA_RX64_DATA_1[7:0]
the port ID.
software register bit in address 0x30920. When this bit is set to ‘0’, (default)
the empty flag indicates truly empty.
When this bit is set to ‘1’, the empty flag indicates that the FIFO is 1/4 full -1.
73
Description
ORCA ORSPI4 Data Sheet