ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 164

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 47. Memory Map (Continued)
Lattice Semiconductor
30917 A
30A17 B
30920 A
30A20 B
SPI4 Core TX Control Registers (Read and Write)
30921 A
30A21 B
30922 A
30A22 B
30923 A
30A23
30924 A
30A24 B
Address
Abso-
(0x)
lute
[0:1]
[2]
[3]
[4]
[5]
[6]
[7]
[0:3}
[4:7]
[0:7]
[0:5]
[6:7]
[0:7]
[0:7]
Bit
Reserved
RX_CAL_MEM_SEL 00
RX_PDM_MEM_SEL
TX_CAL_MEM_SEL
TX_PDM_MEM_SEL
TX_CRED_MEM_SE
L
TX_STAT_MEM_SEL
TX_DPRAM_FULL_T
YPE_SEL
RX_DPRAM_EMPTY
_TYPE_SEL
TX_CAL_M_MAIN
Reserved
TX_CAL_LEN_MAIN 00
TX_CAL_LEN_MAIN
TX_CAL_M_SHD
Name
00
00
00
Reset
Value
(0x)
Enables calendar memory for SPI4 RX calendar to be written via
MPI. The RX_CAL memory encompasses address ranges 0 to 2047.
Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are
for the shadow calendar. SPI4 RX Calendar memory is write only.
Enables memory for SPI4 RX port descriptors to be read or written via MPI.
Addresses 0 to 255 valid for this memory.
Each location contains 3 unused bits, 2 BANK_ID bits and 3 PARTITION_ID
bits.
Enables calendar memory for SPI4 TX calendar to be written via
MPI. The TX_CAL memory encompasses address ranges 0 to 2047.
Addresses 0 to 1023 are for the main calendar; addresses 1024 to 2047 are
for the shadow calendar.SPI4 TX Calendar memory is write only.
Enables memory for SPI4 TX port descriptors to be read or written via MPI.
The valid address range is 0 to 1023. The least significant 2 address bits are
used as byte enables.
The upper 8 bits of address represent the port number being configured.
Enables read and write access to TX credits via MPI. The valid memory
address range is 0 to 511. The credit for each port is a 10-bit entity. The
upper 8 of 9 bits of address select which port to read or write. The lowest bit
of address acts as a byte select as follows:
Enables memory for SPI4 TX status to be read or written via MPI. This
memory used address ranges 0 to 255. Each location has six left-most bits
unused and two status bits.
Full level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit and
128-bit mode.
Empty level select for all partitions within bank [0:3]. Valid for 32-bit, 64-bit
and 128-bit mode.
insertions of framing pattern.
Length of main calendar sequence on the TX status frame. These are the
most significant 2 bits of 10 total.
Length of main calendar sequence on the TX status frame. These are the
least significant 8 bits of 10 total.
Number of times the transmit shadow calendar sequence is repeated
between insertions of framing pattern.
Number of times the transmit main calendar sequence is repeated between
00 accesses the PORT_ID (8 bits)
01 accesses PARTITION_ID (3 bits), an unused bit and BURST_VAL (4 bits)
10 accesses 4 unused bits, MB_EN (1 bit), M (1 bit), and BANK_ID (2 bits).
0 accesses the least significant 8 bits of the credit field
1 accesses the most significant 2 bits (right-justified) of the credit field
0 = truly full
1 = 3/4 FIFO lines full +1. E.g.: For a FIFO size of 32, this value will be (3/4 *
0 = truly empty
1 = 1/4 full - 1. E.g.: For a FIFO size of 32, this value will be (1/4 * 32) - 1 = 7
32) + 1 = 25 lines. Each line in the FIFO is always 128 bits of data irrespec-
tive of the aggregation mode
lines. Each line in the FIFO is always 128 bits of data irrespective of the
aggregation mode
164
Description
ORCA ORSPI4 Data Sheet