ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 97

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
The ORSPI4 SPI4 RX interface is also designed to operate at data rates much lower than 622 Mbps. Even though
the OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who
wish to use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ether-
net, etc.). To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE
(Address 30915 in SPIA and 30A15 in SPIB) to ‘1’. This supports data rates in the range of 100 - 200 Mbps. This bit
takes precedence over SPI4_LOW_SPEED_DATA_SEL, since setting this bit to ‘1’ will automatically reset the
dynamic alignment block irrespective of SPI4_LOW_SPEED_DATA_SEL register bit setting.
SPI4 Loopback Modes
There are three forms of loopback supported directly by the ORSPI4 SPI4 blocks.
• High-speed near end loopback: This involves looping back data from the high-speed transmit block TDO serial
• Far end loopback: This involves looping back the 128-bit output data from the RDI block to the 128-bit input of
• Low-speed near end loopback which excludes the high-speed blocks from the loopback path: This involves
Figure 42. High-Speed Near End Loopback
output to the high-speed receive block RDI serial input (See Fig. 42). All of the logic excluding the LVDS buffers
is included in the loopback path. The status path is looped from the output of the RSP block to the TSP block.
This mode is enabled by setting the control register bit SPI4_LOOPBK_HS to 1.
the TDO block (See Fig. 43). Data is received at the high-speed SPI4 RX interface and transmitted at the SPI4
TX interface. The status path is looped from TSTAT to RSTAT. This mode is enabled by setting control register bit
SPI4_LOOPBK_FE to “1”.
sourcing data from the FPGA, looping back the output of TDP block into RDP block and observing data at the
core-FPGA boundary (See Fig. 44). The status path is looped from the RSP block to the TSP block. This form of
loopback will require an additional low-speed clock source (TSTCLK) and is enabled by setting control register
bit SPI4_LOOPBK_LS to “1” and enabling SPI4_LOOPBK_HS.
Embedded Core
Port Status
Sequencer
+ associated
Sequencer
+ associated
Port write
DPRAMs
DPRAMs
logic
logic
RX
TX
97
TSP
RDP
TDP
RSP
clk
data+ctl
data+ctl
128-bit
128-bit
clk
clk
ORCA ORSPI4 Data Sheet
RDI
TDO
SPI4 I/F
TDAT[15:0]
TCTL
TDCLK
TREFCLK
TSTAT[1:0]
TSCLK
RDAT[15:0]
RCTL
RDCLK
RSTAT[1:0]
RSCLK