ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 183
ORSPI4-2FTE1036I
Manufacturer Part Number
ORSPI4-2FTE1036I
Description
FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
Manufacturer
Lattice
Datasheet
1.ORSPI4-2FTE1036I.pdf
(263 pages)
Specifications of ORSPI4-2FTE1036I
Product Category
FPGA - Field Programmable Gate Array
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
FPTBGA-1036
Minimum Operating Temperature
- 40 C
Factory Pack Quantity
60
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Table 63. Status Path Interface ORSPI4 Timing in Centered (OIF) Mode
Note: This table compares the OIF Specification requirements vs. the ORSPI4 Specification. There is no OIF Specification for LVDS buffers.
Figure 95. ORSPI4 Static Mode Status Signals Data Capture (Reference Point D)
Symbol
t
t
—
f
t
f
dia
dib
t
D
S
S
H
Reference Point D
TSTAT/
RSTAT
TSCLK/
RSCLK
TDCLK/RDCLK frequency
TSCLK/RSCLK frequency
TSCLK/RSCLK duty cycle
RSTAT invalid with respect to clock edge
(Reference point C)
RSTAT invalid with respect to clock edge
(Reference point C)
Setup time for TSTAT with respect to TSCLK -
LVTTL Buffers (Reference point D)
Setup time for TSTAT with respect to TSCLK -
LVDS Buffers (Reference point D)
Hold time for TSTAT with respect to TSCLK -
LVTTL Buffers (Reference point D)
Hold time for TSTAT with respect to TSCLK -
LVDS Buffers (Reference point D)
Description
LVTTL
LVDS
LVTTL
LVDS
SPI_STAM
STATUS_IO_SEL
0
1
0
1
183
Min
2.0
0.5
Requirements
OIF-SPI4-02.0
40
—
—
—
—
—
—
Specification
0
1
112.5
Max
450
2.5
1.0
60
—
—
—
—
Centered (OIF) Mode
ORCA ORSPI4 Data Sheet
ORSPI4 Timing in
D
Min
1.0
1.0
0.5
0.7
40
—
—
—
—
112.5
Max
0.30
0.45
450
60
—
—
—
—
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
%
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