ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 137

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Figure 72. Write Data and Instruction Word Formats
The user starts a write cycle by writing data to the WDFIFO. The maximum data length is 63 lines deep and the
minimum is one 72-bit data word (or one line). The user provides the instruction word associated with a data string
during the write period for the last word of the data. This sequence can continue to repeat as long as the
MC_WxFIFO_FULL flags from the embedded core remain inactive. Once the MC_WIFIFO_FULL flag is asserted,
the user may send data words to the WDFIFO locations (assuming the MC_WDFIFO_FULL flag has not been
asserted) and write one last instruction word to the instruction FIFO as the last data word is written into the data
FIFO.
The timing diagram for the write interface for a typical write sequence is shown in Figure 73. The write sequence in
this case consists of writing 32 words to location A0 followed by one word each to locations A1, A2, A3 and A4. The
MC_WIFIFO_FULL is asserted after the instruction for location A2 has been written, indicating that only one more
instruction may be written to the instruction FIFO. The write to location A4 cannot occur until the
MC_WIFIFO_FULL flag is deasserted. The MC_WDFIFO_FULL flag remains low in this case since the full thresh-
old for the data FIFO has not been reached
Figure 73. ORSPI4 Memory Controller Interface to FPGA — Write Timing Diagram
In the first clock cycle, the first word of the data burst is written along with the ID bit value of 00. The instruction
word is updated on the last word of a data burst and contains the ID bit value, address and length of the data burst.
The maximum burst length is set by the depth of the data FIFO, which is 64 FIFO lines. The data length in the
F_MC_WCLK
F_MC_WDFIFO_WE
F_MC_WD(73:72)
F_MC_WD(71:0)
F_MC_WIFIFO_WE
F_MC_WI(25:24)
F_MC_WI(23:18)
F_MC_WI(17:0)
MC_WIFIFO_FULL
31
73
Reserved
D0-0
ID bits
30
00
...
29
72
ID bits
D0-31
71
D*32
00
A0
28
27
Write Instruction Word
Reserved
Write Data Word
24
Write Data
137
D1-0
D*1
23
01
01
A1
Data length
D2-0
D*1
A2
10
10
18
D3-0
11
D*1
17
A3
11
Address
ORCA ORSPI4 Data Sheet
0
0
D4-0
D*1
A4
00
00