ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 128

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
• FMPU_RESYNC2_2 for twin channel [C:D]
To resynchronize an independent channel (resetting the write and the read pointer of the FIFO) set the following
bit to zero, and then set it to one:
• FMPU_RESYNC1_x
SERDES Multi-Channel Alignment Sequence
1. Follow steps 1 and 2 in the start up sequence described in a later section.
2. Initiate a SERDES software reset by setting the SWRST bit to “1” and then to “0”. Note that, any changes to the
3. Wait for 3 ms. REFCLK should be toggling by this time. During this time, configure the following registers.
Set the following bit in register 30820
Monitor the following status/alarm bits:
Monitor the following status bits in registers 30804:
4. Write a “1” to the appropriate resync register 30820. Note that this assumes that the previous value of the
SERDES configuration bits should be followed by a software reset.
– XAUI_MODE_x - set to “1” for XAUI mode or keep the default value of 0 if the Fibre Channel state machine
– Enable channel alignment by setting FMPU_SYNMODE bits in registers 30811
– FMPU_SYNMODE_x. Set to appropriate values for 2, or 4 alignment based on Table 36.
– Set RCLKSEL and TCKSEL bits in registers 30821.
– RCKSEL - Choose clock source for 78 MHz RCK78 (Table 33).
– TCKSEL - Choose clock source for 78 MHz TCK78 (Table 32). Send data on serial links.
– Monitor the following alarm bits in registers 30000, 30010, 30020, 30030,.
– LKI-PLL_x lock indicator. A “1” indicates that PLL has achieved lock.
– XAUISTAT_x - In XAUI mode, they should be 10.
– Monitor the following status bits in registers 30805
– DEMUXWAS_x - They should be “1” indicating word alignment is achieved.
– CH248_SYNCx - They should be “1” indicating channel alignment. This is cleared by resync.
resync bits are “0”. The resync operation requires a rising edge. Two writes are required to the resync bits: write
a “0” and then write a “1”. It is highly recommended to precede a resync with a word alignment, especially in sit-
uations where a disturbance in the receive SERDES path can cause misalignment of data and OOS indica-
tions without bringing the FC/XAUI state machine to a loss of sync state. A word alignment is achieved by
writing a “0” and then a “1” to the appropriate DOWDALIGNx bits in registers 30810.
was selected.
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ORCA ORSPI4 Data Sheet