ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 135

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Memory Controller Functional Description
The ORSPI4 device includes a Memory Controller interface to an external second generation Quad Data Rate
(QDRII) memory. This is provided for additional data buffering beyond the embedded DPRAMs. In this case, the
embedded DPRAMs are used as clock-crossing domain FIFOs. The key requirement for this memory interface is
the support of a throughput of greater than 20 Gbits/s so that all the data received on the SPI4 interface at 10
Gbits/s can be buffered. A QDRII SRAM supports this throughput with 32 unidirectional data lines. A 36-bit inter-
face is provided to allow for parity or control bits to be added.
The controller block provides the ability to access an external QDRII SRAM through the FPGA. A set of 72 input
data and 72 output data signals are available across the core-FPGA interface. Of the 72 signals, eight can be used
either for parity or for data. The core passes the data transparently to and from the QDRII SRAM in two-word or
four-word bursts. The data interfaces to memory are 36 bits wide and the address bus is 18 bits wide. This supports
the interfaces required for a 512K x 36 bit (18 Mbit) QDRII SRAM.
The basic blocks of the Memory Controller are:
• FIFOs for Write Data and Instructions
• FIFOs for Read Data and Instructions
• Read and Write Controllers (including FIFO and memory interface state machines)
• Address Multiplexer (MUX)
• Write Data DEMUX and Read Data Capture/MUX Blocks
A logical block diagram of the Memory Controller is shown in Figure 71. Details of the individual blocks are outlined
in the following sections. The blocks are described in sequence for a write from the FPGA and a subsequent read
to the FPGA.
Figure 71. ORSPI4 QDRII Memory Controller Block Diagram.
MC_RDFIFO_EMPTY
F_MC_WDFIFO_WE
MC_WDFIFO_FULL
F_MC_WIFIFO_WE
F_MC_RDFIFO_RE
F_MC_RIFIFO_WE
FPGA_RESET_MC
MC_WIFIFO_FULL
MC_RIFIFO_FULL
FPGA
Logic
F_MC_REFCLK
F_MC_WCLK
MC_SYSCLK
F_MC_RCLK
F_MC_WD
F_MC_WI
F_MC_RI
MC_RD
74
32
32
72
Write Clock
Read Clock
Full
WE
Full
WE
Full
WE
Empty
RE
MCREFCLK
ATREFCLK
BTREFCLK
Write Instruction
Read Instruction
Write Data
Read Data
FIFO
FIFO
FIFO
FIFO
RST
RST
RST
RST
Select
Clock
#1
ORSPI4 QDR II Core
Empty
Empty
Empty
32
32
Full
WE
72
RE
RE
RE
74
135
COUT = CIN * N/M
COUT = CIN / 2
Controller
Controller
Read
Write
PLL
RST
RST
2
72
Enable
Enable
Write Enable
Read Enable
18
18
Clock Select
Read Data
Write Data
Address
Capture
Demux
Mux/
Mux
#2
RST
RST
RST
ORCA ORSPI4 Data Sheet
ORSPI4
Device
PMIWN
PMIRN
PMID
PMIQ
PMIC
PMIK
PMIA
36
18
36
External
Memory
SA
K
D
W#
R#
Q
CQ
SDRAM
QDRII