ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 13

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
In addition to formatting received data and sending it to the FPGA logic, the receive block also sends status infor-
mation to the SPI4 status interface.
The Port Status Sequencer (PSS) block is responsible for providing port status to the SPI4 Receive Status block
logic according to a pre-configured calendar sequence. Status is derived from the fill-levels of the DPRAM FIFOs
and/or from the FPGA status interface.
The SPI4 Receive Status block is responsible for FIFO status encoding, calendar management, status pattern
encoding (sync bits “11”), DIP-2 calculation and optional calendar selection word encoding.
The SPI4 Receive Status block contains the low speed LVTTL output buffers and LVDS output buffers necessary
for the output stage of receive status logic. The option to choose between LVTTL or LVDS outputs is done by set-
ting a control register bit.
SPI4 Debugging and Statistics Gathering Support
There are also several other features, including three loopback modes incorporated into the embedded core to
assist in debugging and statistic gathering. These features involve both the transmit and receive paths.
The three forms of loopback supported directly are:
• High-speed near-end loopback
• Far-end high-speed loopback
• Low-speed near-end loopback
The SPI4 blocks support the following error insertion and status reporting options for testing:
• DIP-4 odd parity is calculated over data and control words and inserted on the TX side. DIP-4 errors can be
• DIP-2 odd parity is calculated over the status frames and inserted on the RX side. DIP-2 errors can be forced by
• Eight-bit counters are provided for counting DIP-4 and DIP-2 errors.
• Deskew error reporting for high-speed RX side dynamic alignment. This can cause an alarm.
• DPRAM FIFO overrun reporting. These can cause an alarm.
forced by inverting the DIP-4 parity bits. DIP-4 parity is then checked at the receive interface.
inverting the DIP-2 parity bits. DIP-2 parity is then checked at the transmit status interface.
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ORCA ORSPI4 Data Sheet