ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 11

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
ORCA ORSPI4 Data Sheet
which corresponds to the maximum number of ports that are supported by SPI4. The PDM data is comprised of
three separate segments - a 10-bit dynamic table maintained by the SPI4 logic, a static 20-bit table, and a dynamic
3-bit register file written by the FIFO Status Update (FSU) logic. The PDM provides a mapping of the SPI4 port
number to the FPGA interface device/port number, removing the burden from FPGA logic.
When port data is read from the PDM, a status update bit (the U-bit) is first examined to see whether the STAT field
is new or stale. If stale, then the STAT field is not considered for the rest of processing. If the STAT field is new (U-
bit=1) the STAT field is used in conjunction with other field to calculate what the new Credit field for the port should
be.
A SATISFIED status indicates the corresponding port's FIFO is almost full, and only transfers using the remaining
previously granted 16-byte blocks (if any) may be sent to corresponding port until the next status update. No addi-
tional transfers to that port are permitted.
When a HUNGRY status indication is received, transfers up to MAXBURST2 16-byte blocks or the remainder of
what was previously granted (whichever is greater), may be sent to the corresponding port prior to the next status
update. A STARVING status indication indicates that buffer underflow is imminent in the corresponding PHY port.
When STARVING is received, transfers for up to MAXBURST1 16-byte blocks may be sent to the corresponding
port prior to the next status update.
If the U-bit is cleared, this indicates the STAT field has already been used to update the Credit field on a previous
Port servicing. Therefore, the Credit field should simply be reduced by BURST_VAL. Otherwise, the Credit field is
updated to the new Credit value minus BURST_VAL. In both cases, the output of the logic is used to update the
Credit field. If the Credit field is zero, and the STAT field is stale, then the port receives no service. Read accesses
of the port control information need to be optimized to minimize any lost bandwidth due to the Credit field having a
value of zero.
Data read from the DPRAMS is sent to the SPI4 transmit block which is responsible for the following functions:
• Combining the data and control words from the Transmit FIFO into the data format specified in the OIF SPI4
standard.
• DIP-4 calculation and insertion into the payload control word.
• Generation of idle/training control words in programmable intervals.
Training words are used to dynamically align the far end receiver. As long as a disabled status ‘11’ is received on
the SPI4 status channel, the transmit interface block sends continuous training patterns (10 training control words
followed by 10 training data words). When valid status is received on the status channel, user data is normally sent
on the SPI4 data link. However, users can also periodically schedule training patterns in TX_DATA_MAX_T peri-
ods. The training patterns can be repeated TX_ALPHA times. Both TX_ALPHA and TX_DATA_MAX_T are pro-
grammable control register bits.
The SPI4 transmit block contains the high-speed serializer which uses the x8 clock, synthesized by an internal
PLL, to generate the high-speed data from the low-speed 128-bit FIFO data. Data is transmitted off-chip using a
16-bit LVDS data bus - TDAT[15:0], a LVDS control bit - TCTL, and a source synchronous clock - TDCLK.
The 16-bit data bus and control are DDR with respect to TDCLK. In order to support 10 Gbits/s throughput, the
minimum frequency of TDCLK needs to be 622 Mbits/s (311 MHz DDR). To allow considerable margin above this
minimum data rate a maximum frequency of operation of 900 Mbits/s is supported.
The Transmit Status Protocol (S4TSP) block provides the interface to the SPI4 Transmit Status interfaces. These
signals can be either LVDS or LVCMOS buffers. The S4TSP block is responsible for the following functions:
• FIFO Status Decoding and Buffering.
• Framing using the status framing pattern.
• DIP-2 checking of incoming status information.
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