ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 170

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Table 47. Memory Map (Continued)
Lattice Semiconductor
Common Control Registers (Read and Write)
30B20
30B21
Common Status Registers (Read and Write)
30B28
30B29
Address
Abso-
(0x)
lute
[0:3]
[4]
[5]
[6]
[7]
[0:6]
[7]
[0:7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Bit
Reserved
HARD_RESET_FC
SOFT_RESET_MC
SOFT_RESET_S4A
SOFT_RESET_S4B
COM_SPARE_C
FORCE_INT
Reserved
SERDES_INT
MEM_CTRL2_INT
MEM_CTRL1_INT
DPRAM_INT
SPI_B_COR2_INT
SPI_B_COR1_INT
SPI_A_COR2_INT
SPI_A_COR1_INT
Name
00
00
00
Reset
Value
(0x)
Hard reset for SERDES block. When set to 1, disabled SERDES logic by
resetting it. Same functionality as interface signal FPGA_RESET_FC
Software reset for Memory Controller block
Software reset for SPIA block
Software reset for SPIB block
Spare common control bits
Force all the enabled status and interrupt bits
Reserved
Signals that an enabled interrupt has come from the SERDES. This is
cleared when read and will only reassert when the underlying event goes
away and comes back.
Signals that an enabled interrupt has come from the Memory Controller
other than the FIFOs. This is cleared when read and will only reassert when
the underlying event goes away and comes back.
Signals that an enabled interrupt has come from the Memory Controller
FIFOs. This is cleared when read and will only reassert when the underlying
event goes away and comes back.
Signals that an enabled interrupt has come from one of the DPRAM FIFO
banks. This is cleared when read and will only reassert when the underlying
event goes away and comes back.
Signals that an enabled interrupt has come from the register 30A1D. This is
cleared when read and will only reassert when the underlying event goes
away and comes back.
Signals that an enabled interrupt has come from register 30A1C. This is
cleared when read and will only reassert when the underlying event goes
away and comes back.
Signals that an enabled interrupt has come from register 3091D. This is
cleared when read and will only reassert when the underlying event goes
away and comes back.
Signals that an enabled interrupt has come from register 3091C. This is
cleared when read and will only reassert when the underlying event goes
away and comes back.
170
Description
ORCA ORSPI4 Data Sheet