ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 4

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
ORCA ORSPI4 Data Sheet
area efficient than FPGA gates. Therefore, an FPSC with an embedded function is gate equivalent to an FPGA with
a much larger gate count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embedded core has been enhanced to allow for a greater number of
interface signals than on previous FPSC architectures. Compared to bringing embedded core signals off-chip, this
on-chip interface is much faster and requires less power. All of the delays for the interface are precharacterized and
accounted for in the ispLEVER Development System.
Series 4 based FPSCs expand this interface by providing a link between the embedded block and the multi-master
32-bit system bus in the FPGA logic. This system bus allows the core easy access to many of the FPGA logic func-
tions including the Embedded Block RAMs and the microprocessor interface.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking
between the FPGA and the embedded core. Many of the special signals from the FPGA, such as DONE and global
set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the
FPGA as a system.
For even greater system flexibility, FPGA configuration RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. Multiple embed-
ded core configurations may be designed into a single device with user-programmable control over which configu-
rations are implemented, as well as the capability to change core functionality simply by reconfiguring the device.
FPSC Design Kit
Development is facilitated by an FPSC design kit which, together with ispLEVER and third-party synthesis and sim-
ulation engines, provides all software and documentation required to design and verify an FPSC implementation.
Included in the kit are the FPSC configuration manager, and compiled Verilog simulation models, HSPICE and/or
IBIS models for I/O buffers, and complete online documentation. The kit's software coupled with the design envi-
ronment, provides a seamless FPSC design environment. More information can be obtained by visiting the Lattice
website at
http://www.latticesemi.com .
SPI4 Protocol Overview
The System Packet Interface Level 4, Phase 2 (SPI4) was defined by the Optical Internetworking Forum (OIF) as
an interface for packet and cell transfers between a Physical Layer (PHY) device and a link layer device for applica-
tions requiring up to 10 Gbit/s aggregate bandwidth. The system level model for the SPI4 interface is shown in Fig-
ure 2.
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