ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 108

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Figure 49. Basic Logic Blocks, Transmit Path, Single Channel (Typical Reference Clock Frequency)
SERDES/FPGA Logic Interface and 4:1 Multiplexer
These blocks provide the data formatting and transmit data and clock signal transfers between the SERDES and
the FPGA Logic. Control and status registers in the FPGA portion of the chip control the transmit logic and record
status. These bits are passed to the core using the FPGA System Bus and are described in later sections of this
data sheet.
The low-speed transmit interface consists of a clock and 4 data bytes, each with an accompanying control bit. The
data bytes are conveyed to the MUX via the TWDx[31:0] ports (where x represents the channel label [A,B,C or D].
The control bits are TCOMMAx[3:0] which define whether the input byte is to be interpreted as data or as a special
character and TBIT9x[3:0] which are used to force a negative disparity present state. The data and control signals
are synchronized to the transmit clock, TSYS_CLK_x. Both the data and control are strobed into the core on the
rising edge of TSYS_CLK_x. Note that each TBIT9x[3:0] controls the disparity of the encoded version of its corre-
sponding data byte. Setting bit TBIT9C[3] to “1”, for instance, will force the 8b/10b encoder to asserts a current neg-
ative running disparity state. This will cause it to encode TWDC[31:24] positively (more “1”'s than “0”'s). Setting
TBIT9x to 0 will leave the encoder free to alternate between positive and negative encoding to maintain a zero run-
ning disparity.
The MUX is responsible for taking 40 bits of data/control at the low-speed transmit interface and up-converting it to
10 bits of data/control at the SERDES transmit interface. The MUX has two clock domains - one based on the clock
received from the SERDES block and a second that comes from the FPGA at 1/4 the frequency of the SERDES
clock. The time sequence of interleaving data/control values is shown in Figure 50.
TWDx[31:0]
TCOMMAx[3:0]
TBIT9x[3:0]
TSYS_CLK_x
FPGA
Logic
TCK78
78.125 MHz
32
4
4
Interface and MUX Block
MUX
FIFO
TCKSEL[0:1]
÷
{
4
4:1 MUX
From other 3
channels
(x9)
Logic Common to Quad
Note: x= [A, B, ... D]
From Control
STBD_x[7:0]
Force-ve disparity
Register
STBC311_x
STBD_x[8]
STBD_x[9]
312.5 MHz
8-bit data
K-control
108
8
To other 3
channels
Encoder
bypass)
8B/10B
PLL
(with
TX SERDES Block
{
PRBS
Gen.
MUX
10:1
ORCA ORSPI4 Data Sheet
emphasis
Buffer
with Pre-
CML
Buffer
CML
REFCLKP
REFCLKN
HDOUTP_x
HDOUTN_x
Backplane
156.25 MHz
Serial
Link