ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 99

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Table 25. Far End Loopback Register Values
Absolute
Address
(SPI A)
(SPI B)
30A15
30915
(Hex)
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6] TX_FORCE_DIP4_ERR
[7] RX_FORCE_DIP2_ERR
SPI4_QUARTER_RATE
SPI4_STATUS_IO_SEL
SPI4_LOW_SPEED_
SPI4_LOOPBK_HS
SPI4_LOOPBK_FE
SPI4_LOOPBK_LS
DATA_SEL
Name
When set to ‘1’, enables data rates of 100 - 200
Mbps. The PLLs in the transmit and receive SPI4
high-speed blocks are bypassed in this mode.
This control enables far-end loopback when it is
set to 1. Far end loopback sends RDAT inputs
back to TDAT outputs, sends RDCLK back to
TDCLK, sends TSTAT back to RSTAT outputs,
and ATSCLK back to RSCLK.
Forces low speed data rates of 400-622 Mbits/s.
The transmit PLL is still used to synthesize the
SPI4 transmit clock TDCLK. However, the
dynamic alignment block in the receive side is
bypassed. No training sequences are used in low
speed mode.
‘0’ - Selects LVTTL I/O for SPI4 status.
‘1’ - Selects LVDS I/Os for SPI4 status (Full-rate
LVDS status I/Os specified by OIF SPI4.0 is not
supported).
Enables loops from high-speed SPI4 TDAT out-
puts to RDAT inputs and RSTAT to TSTAT status
inputs just before I/O.
Enables near-end parallel loopback from TDP to
RDP blocks and RSP to TSP blocks bypassing
the high-speed SPI4 interface logic blocks. Must
enable SPI4_LOOPBK_HS for this to work.
99
Description
ORCA ORSPI4 Data Sheet
Rate Far
Quarter
0 or 1
End
X
X
1
1
1
0
0
Far End
Static
0 or 1
X
X
0
1
1
0
0
Dynamic
Far End
0 or 1
0
1
0
0
0
X
X