ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 142

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
A programmable FIFO empty flag (MC_RDFIFO_EMPTY) is available to the FPGA for the data FIFO. The FIFO
flag threshold is set by the 4-bit software register field MC_EMPTY_THRESHOLD.
Memory Controller Instruction Latency
An example of the instruction latency through the QDR II Memory Controller for write instructions is shown in Fig-
ure 78. For this example, it is assumed that the clock from the FPGA logic to the Memory Controller
(F_MC_WCLK) is synchronized to the K clock to the external memory. If these clocks are not synchronous, then
the latency may vary.
Figure 78. ORSPI4 QDR II Memory Controller – FPGA to External Memory Latency Example
The latency for read instructions is the same given the same clock relationship conditions.
Memory Controller Status Reporting
The following status or alarms will be reported to the user through software register bits:
• Data length mismatch from the write controller state machine. This alarm bit will be set if a block of data read
• Data-instruction coherency error. This alarm bit will be set if the ID field in write data and its associated write
• Write data, Read data FIFO overrun and underrun errors.
Clocking Schemes and Timing Diagrams- Memory Controller
The Memory Controller Unit requires three clocks:
• MC_WCLK from the FPGA, which controls the FPGA-side accesses to the Write Instruction and Write Data
from the write data FIFO does not match the data length from its associated instruction.
instruction do not match.
Controller
Interface
Memory
Internal
Interface
ORSPI4
External
Memory
FPGA
Logic
to
to
External Memory K Clock
External Memory K Clock
External Memory W#
F_MC_WDFIFO_WE
F_MC_WIFIFO_WE
F_MC_WD(73:72)
F_MC_WI(25:24)
F_MC_WI(23:18)
F_MC_WD(71:0)
F_MC_WCLK =
F_MC_WI(17:0)
D0-0
142
00
...
D0-31
D*32
A0
00
instruction latency
2 K clock cycles
ORCA ORSPI4 Data Sheet
W1