ORSPI4-2FTE1036I Lattice, ORSPI4-2FTE1036I Datasheet - Page 67

• Manufacturer Part Number: ORSPI4-2FTE1036I
• Description: FPGA - Field Programmable Gate Array ORCA FPSC 1.5V SPI4 Interface
• Manufacturer: Lattice

Specifications of ORSPI4-2FTE1036I

• Product Category: FPGA - Field Programmable Gate Array
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: FPTBGA-1036
• Minimum Operating Temperature: - 40 C
• Factory Pack Quantity: 60

Lattice Semiconductor
Figure 28. Data: ATX_PORTID[7:0], BTX_PORTID[7:0], ATX_STAT[1:0], BTX_STAT[1:0], ABURST_VAL[3:0],
SPI4 Transmit Software Interface
The SPI4 transmit interface is configurable through a System Bus interface incorporated within the embedded core.
The user can gain access to the System Bus either through the integrated MPI interface, or through FPGA
resources using the System Bus Master/Slave interface. Please refer to the appropriate Lattice Semiconductor
data sheets and application notes for more information regarding these interfaces.
The Transmit SPI4 interface logic incorporates many configurable control registers, as well as interrupt and status
registers to monitor SPI4 performance. Table 47 provides a memory map and description of each register within
the Transmit portion of the SPI4 embedded core.
Special Operating Modes
Quarter-Rate Mode
The ORSPI4 SPI4 TX interface is designed to operate at data rates much lower than 622 Mbps. Even though the
OIF standard specifies a minimum data rate of 622 Mbits/s, the lower data rates are provided for users who wish to
use the SPI4 link for applications supporting <10 Gbits/s aggregate bandwidth (STS-48, STS-3, Gb Ethernet, etc.).
To enable this low speed mode, user should set the software register bit SPI4_QUARTER_RATE (Address 30915
in SPIA and 30A15 in SPIB) to ‘1’. This supports data rates in the range of 100 - 200 Mbps. Note that the normal
operating modes 32-bit, 64-bit and 128-bit are independent of the quarter-rate mode. In quarter-rate mode, the
transmit PLL is held in reset by setting the MRESET hardware pin to ‘1’. The PLL bypass mode is enabled by set-
ting the BYPASS pin to ‘1’ which causes the SPI[A,B]_TREFCLK_X8 clock from the FPGA to be used as the trans-
mit reference clock. It must be two- times the desired Transmit SPI4 line clock rate. When not operating the
Transmit SPI4 core in quarter-rate mode, this signal should be tied off. Ex: For a 100 MHz Transmit SPI4 line clock,
SPIA_TREFCLK_X8 from the FPGA must be 200 MHz.
NOTE: Delays represent average max/min values, not absolute values
BTREFCLK_F
ATREFCK_F
Actual delay values are used by ispLEVER
Clock: ATREFCLK, BTREFCLK
D
BBURST_VAL[3:0]
4.0/1.0 ns
3.5/0.5 ns
FPGA
Clock Buffer Delay
Relative to Data
Buffer
Delay
Embedded Core
D
C
1.36/ 0.47 ns
Delay
67
(includes ck to Q)
5.4 / 2.1 ns
Q
ORCA ORSPI4 Data Sheet
D
Clock Insertion
Delay = 6.8 / 2.4 ns
(from off-chip)
TREFCLK